MCP3462 datasheet(73/108 Pages) MICROCHIP

73 / 108 page

 2019-2021 Microchip Technology Inc.

DS20006180D-page 73

MCP3461/2/4

6.8.1

CONVERSION DATA READY

INTERRUPT

The data ready interrupt happens when a new conver-

sion is ready to be read on the ADCDATA register. This

event happens synchronously with DMCLK and at

each end of conversion. This interrupt is implemented

with three different and independent mechanisms:

STATUS byte on SDO, IRQ register Status bit and IRQ

pin state.

STATUS byte on SDO. When the interrupt

happens, on the next STATUS byte transmitted

on SDO, the DR_STATUS bit is logic low. Once

the STATUS byte has been transmitted, the

DR_STATUS bit appears as ‘1’ until a new

interrupt will be present. If between two STATUS

byte transmissions, the interrupt happens once

again, the DR_STATUS bit on SDO will appear

as ‘0’ on the second reading.

IRQ register Status bit. When the interrupt

happens, the DR_STATUS bit in the IRQ register

will be set to ‘0’. Once the IRQ register has been

fully read, this DR_STATUS bit is reset again to

‘1’. If between two readings of the IRQ register,

the interrupt happens once again, the IRQ

the second reading.

IRQ pin state. The interrupt generates an IRQ

pin falling edge (transition to logic low) as soon

as it happens.

The data ready interrupt is cleared by the first event of

the following two events:

• First falling edge of SCK during an ADC Output

Data register read

• 16 DMCLK clock periods before current

conversion ends

If the user does not read the ADCDATA register in time

in Continuous Conversion mode or in SCAN mode, the

IRQ pin will automatically reset to its inactive state

16 DMCLK periods prior to the new data ready inter-

rupt. This feature is designed to avoid the case in which

the IRQ pin output would always be logic low if the

reading of the ADC data were not performed. The user

can determine exactly when to expect new data and

can respect the tDODR timing in all cases to ensure

proper reading of the ADC data. See Figure 6-14 for

more details.

FIGURE 6-14:

Data Ready Interrupt IRQ Pin Timing Diagram.

SPI

IRQ

TCON V

Transition Time

tDOD R

Read A DC DATA1

1/DRCLK

TDRH

DATA1 can be Read Dur ing this Time

IRQ is Cleared

at First SCK Falling Edge After

ADCDATA Read Start

ADCDATA

DATA1

DATA0

IRQ is Cleared

if ADCDATA has Not

been Read in Time

Read ADC DATA2

1/DRCLK

TDRH

DATA2 can be Read Dur ing this Time

DATA2

Data Ready Interrupt

COMM AN D By te

Read A DCDATA

COMM AN D By te

Read A DCDATA

Transition Time

tDOD R

MCP3462 Datasheet(PDF) 73 Page - Microchip Technology

MCP3462 Datasheet(HTML) 73 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL