ACE25QC200GLTMTH datasheet(26/64 Pages) ACE

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ACE25QC200GL

2M BIT SPI NOR FLASH

VER 1.1

Fast Read Dual I/O (BBh)

The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins,

SI and SO. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the

Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code execution

(XIP) directly from the Dual SPI in some applications.

Fast Read Dual I/O with “Continuous Read Mode”

The Fast Read Dual I/O instruction can operate at the highest possible frequency of fC (see AC Electrical

Characteristics). The Fast Read Dual I/O instruction can further reduce instruction overhead through

setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23- 0), as shown in Figure 12.

The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the

inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care

(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is

raised and then lowered) does not require the BBh instruction code, as shown in Figure13. This reduces

the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS

is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after

/CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation.

It is recommended to input FFh on SI for the next instruction (16 clocks), to ensure M4 = 1 and return the

device to normal operation.

Figure12. Fast Read Dual I/O Instruction (Initial instruction or previous M5-

4≠10)

ACE25QC200GLTMTH Datasheet(PDF) 26 Page - ACE Technology Co., LTD.