ACE25QC200GLTMTH datasheet(40/64 Pages) ACE

40 / 64 page

ACE25QC200GL

2M BIT SPI NOR FLASH

VER 1.1

64KB Block Erase (D8h)

The 64KB Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state

of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the 64KB Block

Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin

low and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0). And the address

A15-A0 is an unrelated item and has no effect on the result of the instruction. The 64KB Block Erase

instruction sequence is shown in Figure31.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the

64KB Block Erase instruction will not be executed. After /CS is driven high, the self- timed 64KB Block

Erase instruction will commence for a time duration of tBE2 (See AC Characteristics) . While the 64KB

Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking

the status of the WIP bit. The WIP bit is a 1 during the 64KB Block Erase cycle and becomes a 0 when the

cycle is finished and the device is ready to accept other instructions again. After the 64KB Block Erase

cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The 64KB Block

Erase instruction will not be executed if the addressed page is protected by the Block Protect (BP4, BP3,

BP2, BP1, and BP0) bits.

Figure31. 64KB Block Erase Instruction

ACE25QC200GLTMTH Datasheet(PDF) 40 Page - ACE Technology Co., LTD.