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ACE25QC200GLTMTH Datasheet(PDF) 10 Page - ACE Technology Co., LTD. |
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ACE25QC200GLTMTH Datasheet(HTML) 10 Page - ACE Technology Co., LTD. |
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10 / 64 page  ACE25QC200GL 2M BIT SPI NOR FLASH VER 1.1 10 Status Register Status Register Table Table3. The Status and Control Bits SR2 S15 S14 S13 S12 S11 S10 S9 S8 SUS1 CMP LB3 LB2 LB1 SUS2 QE SRP1 Default value Note1 n/a 0 0 0 0 n/a 0 0 SR1 S7 S6 S5 S4 S3 S2 S1 S0 SRP0 BP4 BP3 BP2 BP1 BP0 WEL WIP Default value Note1 0 0 0 0 0 0 n/a n/a Notes: 1. The default value is set by Manufacturer during wafer sort, Marked as Default in following text The status and control bits of the Status Register are as follows: (A) WIP bit The Write in Progress (WIP) bit indicates whether the memory is busy in program / erase / write status register progress. When WIP bit is set to 1, means that the device is busy in program / erase / write status register progress, when WIP bit is cleared to 0, means that the device is not in program / erase / write status register progress. Figure1. Hold condition activation |
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