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ACE25QC200GLTMTH Datasheet(PDF) 41 Page - ACE Technology Co., LTD. |
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ACE25QC200GLTMTH Datasheet(HTML) 41 Page - ACE Technology Co., LTD. |
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41 / 64 page  ACE25QC200GL 2M BIT SPI NOR FLASH VER 1.1 41 Chip Erase (C7h / 60h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure32. The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the WIP bit. The WIP bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any memory region is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits. Figure32. Chip Erase Instruction for SPI Mode |
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