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AT25SL321 Datasheet(PDF) 20 Page - Dialog Semiconductor |
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AT25SL321 Datasheet(HTML) 20 Page - Dialog Semiconductor |
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20 / 82 page  19 AT25SL321 DS-25SL321–112H–2020-10 8.3 Write Enable for Volatile Status Register (50h) This instruction provides additional flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Execution of the Write Enable for Volatile Status Register instruction (Figure 8-2) does not set the Write Enable Latch (WEL) bit. Once the Write Enable for Volatile Status Register instruction is executed, a Write Enable instruction can not have been issued prior to setting Write Status Register instruction (01h or 31h). When the Write Enable for Volatile Status Register (50h) is set in QPI Mode, the SUS bit (S15) and Reserved bits (S13, S12, S11 and S10) of the Status Register-2 must be driven to high after a Write Status Register instruction (01h). Once a Read Status Register (05h or 31h) is issued, the read values of SUS bit (S15) and Reserved bits (S13, S12, S11 and S10) of the Status Register-2 are ignored. Figure 8-2. Write Enable for Volatile Status Register Instruction for SPI Mode (left) and QPI Mode (right) |
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