AT25SL641 datasheet(27/76 Pages) DIALOG

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AT25SL641

DS-25SL641–113F–12/2018

7.12

Fast Read Quad Output (6Bh)

By using four pins (IO0, IO1, IO2, and IO3), the Fast Read Quad Output instruction allows data to be transferred from the

AT25SL641 at four times the rate of standard SPI devices. Prior to executing the 6Bh instruction, the Quad Enable (QE) bit of

Status Register 2 must be set

The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC Electrical

Characteristics). This is accomplished by adding eight dummy clocks after the 24- bit address as shown in Figure 7-15.

The dummy clocks allow the internal circuits the time required to set up the initial address. During the dummy clocks,

the data value on the SO pin is a “don’t care”. However, the IO

0 pin should be high-impedance prior to the falling edge

of the first data out clock.

Figure 7-15. Fast Read Quad Output Instruction (SPI Mode)

7.13

Fast Read Dual I/O (BBh)

The Fast Read Dual I/O instruction reduces cycle overhead by using two IO pins: IO0 and IO1 to transfer data.

Continuous Read Mode

The Fast Read Dual I/O instruction s u p p o r t s a c o n t i n u o u s r e a d m o d e u s i n g the Mode bits (M7-0), which are

shifted into the device after address bits (A23-0). The upper nibble of the Mode (M7-4) controls whether the instruction

code must be driven to the device on subsequent access. If the Mode bits (M7-0) equal “Ax” hex, then the next Fast

Dual I/O instruction (after CS is raised and then lowered) does not require the instruction (BBh) code, as shown in Figure

7-16 and Figure 7-17. This reduces the instruction sequence by eight clocks and allows the address to be

immediately entered after CS is asserted low.

AT25SL641 Datasheet(PDF) 27 Page - Dialog Semiconductor