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DA9072

Ultra-Low Quiescent Current PMIC

Datasheet

Revision 3.0

14-Jun-2021

CFR0011-120-00

46 of 113

Figure 28 shows how to periodically feed the watchdog and what happens when the processor stalls.

VBAT_UVLO_THR

BAT

SYS

tWATCHDOG

Host stalls

Figure 28: Watchdog Behavior

4.8.2

VDDIO

VDDIO is the I/O supply rail for DA9072. I2C communication (SDA, SCL), MODE, WD, ROUT_N,

SYS_FLT, and PWR_FLT pins are all referenced to the VDDIO level.

VDDIO is an input pin, which can be supplied with any voltage between 1.4 V and 3.3 V as required

to interface with the host. However, the VDDIO voltage must not be higher than the VDD_PWR and

VBAT voltages. Therefore, it is recommended to use the buck or LDO output to supply VDDIO. The

VDDIO pin should be bypassed with a 1 µF capacitor, placed close to the pin and grounded to

AGND.

4.8.3

Interrupt Events and Status Control

DA9072 has an interrupt interface for 35 individual events. Some of these events are categorized as

charge fault events, see Section 4.4.7.

There is a read-only event bit for each interrupt in the SYS_ISR_<n> registers 0x0003 through

0x0007. A high state indicates that an event has occurred. The bit is kept in a high state, even if the

fault condition is removed, until the bit is cleared. These are read-to-clear bits which are read once to

identify the event and read a second time to reset the bit to 0.

The DA9072 provides two open drain output pins to indicate system status and interrupts, SYS_FLT

and PWR_FLT. These should be pulled up to VDDIO with a 1 k

Ω to 100 kΩ resistor. Both pins have

configuration options, set by PWR_FLT_MODE (register 0x0011 [4]) and SYS_FLT_MODE (register

0x0011 [0]).

The PWR_FLT output can be configured as an indicator of the VDD_PWR status, or as a level-

shifted RIN_N monitor, see Figure 29 and Figure 30.

When used as a level shifted RIN_N monitor, there is a typical delay of 1.5 ms between RIN_N and

PWR_FLT signals.

In the case of VDD_PWR status indicator, PWR_FLT goes low only when VDD_PWR is within a

valid range. In both cases a high state is high impedance.

RIN_N

PWR_FLT

Figure 29: PWR_FLT Configured as RIN_N Monitor

DA9072 Datasheet(PDF) 46 Page - Dialog Semiconductor

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