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DA9072

Ultra-Low Quiescent Current PMIC

Datasheet

Revision 3.0

14-Jun-2021

CFR0011-120-00

38 of 113

To reset the safety timer and resume charging after the timer has expired, toggle the MODE pin or

the CE_N bit (register 0x0020 [0]), or remove and re-connect VDD_PWR.

Charge faults may cause the timer duration to be doubled, suspended, or reset, see Table 27. The

timer doubling function can be doubled using the TMRX2_EN bit (register 0x0021:[3]).

Table 27: Safety Timer Register Settings (0x0021)

TMR

Pre-Charge Timer

Main Timer

0x0

3 min

30 min

0x1

18 min

3 h

0x2

54 min

9 h

0x3

(Disable)

4.5

USB Powered Operation and Power Path Management

The DA9072 monitors battery voltage and current as well as VDD_PWR input voltage and current

during all modes of operation. At all levels of operation, the appropriate charge current is maintained

while protecting the battery, system connections, and the input supply from over-voltage and over-

current and other potential fault conditions.

The DA9072 power path management features ensure smooth transitions from charging, to reduced

charging, to battery supplementing the load during load peaks.

4.5.1

Under-Voltage Lockout

The UVLO threshold for VDD_PWR is 3.6 V (typical). Below this voltage, VDD_PWR is disconnected

from the power path and DA9072 is in battery powered operation. VDD_PWR UVLO causes

SYS_FLT to toggle and sets event bit ISR_VDD_PWR_UVLO (register 0x0003 [1]) = 1.

The UVLO threshold has typically 150 mV of hysteresis on the rising edge. When VDD_PWR rises

above this threshold, charging is re-enabled. UVLO recovery also toggles the SYS_FLT interrupt and

sets the UVLO recovery event bit.

4.5.2

Sleep Mode

Sleep mode behavior is similar to UVLO, but the falling threshold is relative to VBAT. When

VDD_PWR falls within 65 mV (typical) of VBAT, Sleep mode is activated. In Sleep mode, VDD_PWR

is disconnected from the power path, SYS_FLT toggles, and event bit ISR_SLP (register 0x0005 [0])

= 1. When VDD_PWR falls into the range of Sleep mode, DPPM mode is already active (VDD_PWR

< VBAT_CHG) and the charge current is already reduced to zero, see Section 4.5.5.

4.5.3

VDD_PWR Current Limit

The VDD_PWR current limit (IDDPWR_LIM) feature protects both the DA9072 and the USB supply from

excessive current. The current limit threshold is programmable from 50 mA to 600 mA in 50 mA

steps via bits ILIM (register 0x0027 [3:0]. When the input current reaches the set threshold,

VDD_PWR current is clamped and event bit ISR_VDD_PWR_ILIM (register 0x0003 [4]) = 0x1. If the

load at VDD_SYS increases the VDD_SYS voltage drops, eventually triggering a VDD_SYS UVLO.

The dynamic power management (DPM) function, when enabled, reduces the current limit threshold

as USB input voltage is reduced.

4.5.4

Input Voltage Dynamic Power Management

If the charge current and system load exceed the current capability of the VDD_PWR input source,

the input voltage drops. Dynamic power management (DPM) prevents the input from dropping below

the nominal USB range and into Dynamic Power Path mode (DPPM) by scaling down the VDD_PWR

current limit (IDDPWR_LIM) until it matches current capability of the USB source.

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