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DA9072 Datasheet(PDF) 6 Page - Dialog Semiconductor

Part # DA9072
Description  Ultra-Low Quiescent Current PMIC
PDF  113 Pages
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Manufacturer  DIALOG [Dialog Semiconductor]
Direct Link  http://www.dialog-semiconductor.com/
Logo DIALOG - Dialog Semiconductor

DA9072 Datasheet(HTML) 6 Page - Dialog Semiconductor

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DA9072
Ultra-Low Quiescent Current PMIC
Datasheet
Revision 3.0
14-Jun-2021
CFR0011-120-00
6 of 113
© 2021 Dialog Semiconductor
Table 8: LDO0 / Loadswitch (LV) ........................................................................................................ 14
Table 9: LDO1 / Loadswitch (HV)........................................................................................................ 15
Table 10: LDO2 / Loadswitch (HV+Power cycle) ................................................................................ 16
Table 11: Digital Input Pins (MODE, WD) ........................................................................................... 17
Table 12: I2C interface ........................................................................................................................ 18
Table 13: Input Currents...................................................................................................................... 18
Table 14: Power-Path Management and ILIM..................................................................................... 19
Table 15: Protection ............................................................................................................................ 20
Table 16: Pushbutton Timer (RIN_N) .................................................................................................. 21
Table 17: Digital Output Pins (SYS_FLT, PWR_FLT, and ROUT_N)................................................. 21
Table 18: Buck..................................................................................................................................... 21
Table 19: Battery Monitors (VBAT_DIV and IMON) ............................................................................ 22
Table 20: Thermal Characteristics ...................................................................................................... 23
Table 21: MODE Functionality ............................................................................................................ 30
Table 22: Battery Thermal Protection Measures................................................................................. 31
Table 23: VBAT_DIV Ratios ................................................................................................................ 34
Table 24: Charge Status...................................................................................................................... 34
Table 25: Charging Modes .................................................................................................................. 35
Table 26: Charge Faults ...................................................................................................................... 37
Table 27: Safety Timer Register Settings (0x0021) ............................................................................ 38
Table 28: Power Cycle Trigger Settings .............................................................................................. 40
Table 29: Power Cycle Faults.............................................................................................................. 42
Table 30: BUCK Power Cycle Faults .................................................................................................. 42
Table 31: Enabling External Resistor Setting Mode............................................................................ 42
Table 32: ITER_CHG Pin Recommended Resistor Values ................................................................ 43
Table 33: ILIM_PWR Pin Recommended Resistor Values ................................................................. 43
Table 34: ILIM_CHG Pin Recommended Resistor Values ................................................................. 43
Table 35: Digital Pins for Host and Pushbutton Interface ................................................................... 44
Table 36: Watchdog Timer Enable Settings for Different Modes ........................................................ 45
Table 37: Watchdog Timer Clear Settings .......................................................................................... 45
Table 38: SYS_FLT Configuration ...................................................................................................... 47
Table 39: RIN_N Pushbutton Wake-Up Timer Control ....................................................................... 47
Table 40: RIN_N Reset Timer Configuration....................................................................................... 48
Table 41: I2C Interface Configuration .................................................................................................. 49
Table 42: External Buck Components ................................................................................................. 51
Table 43: System Register Map .......................................................................................................... 55
Table 44: Charger Register Map ......................................................................................................... 57
Table 45: Buck and LDO Control Register Map .................................................................................. 58
Table 46: Register SYS_STS_0 .......................................................................................................... 59
Table 47: Register SYS_ISR_0 ........................................................................................................... 60
Table 48: Register SYS_ISR_1 ........................................................................................................... 60
Table 49: Register SYS_ISR_2 ........................................................................................................... 61
Table 50: Register SYS_ISR_3 ........................................................................................................... 62
Table 51: Register SYS_ISR_4 ........................................................................................................... 62
Table 52: Register SYS_IMR_0 .......................................................................................................... 63
Table 53: Register SYS_IMR_1 .......................................................................................................... 63
Table 54: Register SYS_IMR_2 .......................................................................................................... 64
Table 55: Register SYS_IMR_3 .......................................................................................................... 65
Table 56: Register SYS_IMR_4 .......................................................................................................... 65
Table 57: Register SYS_SYS_0.......................................................................................................... 66
Table 58: Register SYS_BAT_0 .......................................................................................................... 67
Table 59: Register SYS_BAT_1 .......................................................................................................... 67
Table 60: Register SYS_RIN_N_0 ...................................................................................................... 68
Table 61: Register SYS_STS_OUT_0 ................................................................................................ 69
Table 62: Register SYS_PWR_CYC_0 ............................................................................................... 70
Table 63: Register SYS_PWR_CYC_1 ............................................................................................... 71
Table 64: Register SYS_WD_0 ........................................................................................................... 72
Table 65: Register SYS_I2C_0 ........................................................................................................... 73
Table 66: Register SYS_CFG_I2C_0.................................................................................................. 74



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