ZLP12840 datasheet(23/58 Pages) ZILOG

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PS024406-0106

P R E L I M I N A R Y

Port 0

ZLP12840 OTP MCU

Product Specification

Port 0

Port 0 is an 8-bit, bidirectional, CMOS-compatible port. Its eight I/O lines are configured

under software control to create a nibble I/O port. The output drivers are push/pull or

open-drain, controlled by bit 2 of the PCON register.

If one or both nibbles are required for I/O operation, they must be configured by writing to

the Port 0 Mode Register (P01M). After a hardware reset or a stop-mode recovery (SMR),

Port 0 is configured as an input port.

Port 0, bit 7 is used as the transmit output of the UART when UART Tx is enabled.The I/O

function of Port 0, bit 7 is overridden by the UART serial output (TxD) when UART Tx is

enabled (UCTL[7] = 1). The pin must be configured as an output for TxD data to reach the

pin (P0M[6] = 0).

An optional pull-up transistor is available as an OTP option on all Port 0 bits with nibble

select. See the configuration illustration in Figure 4.

00303

Port 3

0Xh

0F6

All

Port 2 Mode Register

P2M

FFh

0F7

All

Port 3 Mode Register

P3M

XXXX_X000b

0F8

All

Port 0 Mode Register

P01M

X1 XX_XXX1b

F00

Port Configuration Register

PCON

XXXX_X1X0b

Table 7. I/O Port Control Registers (Continued)

Address (Hex)

Reset

12-Bit

Bank 8-Bit

Mnemonic

Page #

ZLP12840 Datasheet(PDF) 23 Page - Zilog, Inc.

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