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ZLP12840 Datasheet(PDF) 32 Page - Zilog, Inc. |
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ZLP12840 Datasheet(HTML) 32 Page - Zilog, Inc. |
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32 / 58 page ![]() PS024406-0106 P R E L I M I N A R Y Port 0 Mode Register ZLP12840 OTP MCU Product Specification 21 Port 0 Mode Register The Port 0 Mode Register determines the I/O direction of Port 0. The Port 0 direction is nibble-programmable. Bit 6 controls the upper nibble of Port 0, bits [7:3]. Bit 0 controls the lower nibble of Port 0, bits [3:0]. See Table 11. Only P00, P01, and P07 are available on Crimzon ZLP12840 MCU 20-pin configura- tions. Table 10. Port 0 Mode Register (P01M) Bit 7 6 5 4 3 2 1 0 Field Reserved P07:P04 Mode Reserved P03:P00 Mode Reset X 1 XXXX X1 R/W W W Address Bank Independent: F8h; Linear: 0F8h Bit Position Value Description 7 0 ReservedWrites have no effect. Reads 1b. [6] 0 1 P07:P04 Mode Output. Input. [5:1] ReservedWrites have no effect. Reads 11111b. [0] 0 1 P00:P03 Mode Output. Input. Note: |
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