ZLP12840 datasheet(37/58 Pages) ZILOG

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PS024406-0106

P R E L I M I N A R Y

Port 3 Register

ZLP12840 OTP MCU

Product Specification

Port 3 Register

The Port 3 Register allows read access to port pins P33 through P30 and write access to

the port pins P37 through P34. See Table 15.

Table 15. Port 3 Register (P3)

Bit

Field

P37

P36

P35

P34

P33

P32

P31

P30

Reset

R/W

Address

Banks 03: 03h; Linear: 003h

Bit

Position Value Description

[7]

Write:

Port 3, pin 7 OutputWrites to this bit do not affect the pin state if write-only register

bit PCON[0] has been written with a 1, which configures P37 as the Comparator 1 or

IR Amplifier output.

P37 asserted Low if PCON[0]=0.

P37 asserted High if PCON[0]=0.

A read returns the last value written to this bit.

[6]

Write:

Port 3, pin 6 OutputWrites to this bit do not affect the pin state if register bits

CTR1[7:6]=01, which configures P36 as the Timer 8 and Timer 16 combined logic

output.

P36 asserted Low.

P36 asserted High.

A read returns the last value written to this bit.

[5]

Write:

Port 3, pin 5 OutputWrites to this bit do not affect the pin state if register bit

CTR2[0]=1, which configures P35 as the Timer 16 output.

P35 asserted Low.

P35 asserted High.

A read returns the last value written to this bit.

[4]

Write:

Port 3, pin 4 OutputWrites to this bit do not affect the pin state if write only register bit

PCON[0]=1, which configures P34 as Comparator 2 output, or register bit CTR0[0]=1,

which configures P34 as Timer 8 output.

P34 asserted Low.

P34 asserted High.

A read returns the last value written to this bit.

ZLP12840 Datasheet(PDF) 37 Page - Zilog, Inc.

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