ADP5360ACBZ-1-R7 datasheet(30/60 Pages) AD

30 / 60 page

ADP5360

Data Sheet

Rev. 0 | Page 30 of 60

Short-Circuit Protection

The buck regulator in the ADP5360 includes frequency

foldback to prevent current runaway on a hard short in PWM

mode. When the output voltage at the feedback pin (FB1) falls

lower than 50% of VOUT1 typical, indicating the possibility of a

hard short at the output, the switching frequency is reduced to

half of the internal oscillator frequency. The reduction in the

switching frequency allows more time for the inductor to

discharge, preventing a runaway of output current.

Stop Switching

The ADP5360 includes one STP pin that can be configured as a

stop pin to allow the user to temporarily stop the buck regulator

switching.

When applying a logic high level to the STP pin, the corresponding

regulator is forced to stop switching immediately. When

applying a logic low level to the STP pin, the regulator resumes

switching. Note that tens of ns delay time exists from when the

STP signal goes high to when switching fully stops.

The stop signal control is valid only when the regulator is

enabled. Otherwise, the stop signal is ignored.

Using the stop signal for hysteresis mode can generate a power-

good failure due to the slow transient response.

Set the STP_BUCK bit, Register 0x29, low to disable the buck

regulator stop switching feature.

OUTPUT VOLTAGE

DC-TO-DC

SWITCHING

STP

LOAD

PULSE

100mA

150µs

BATTERY

CURRENT

LIMIT BATTERY

CURRENT

LOAD CURRENT

NO SWITCHING

Figure 54. STP Signal Diagram

BUCK BOOST REGULATOR OPERATION

Operation Mode

The buck boost regulator in the ADP5360 is synchronous with

the current mode, switching regulators designed to maintain a

fixed output voltage from an input supply (VIN2) that can be

greater than, equal to, or less than VOUT2.

The buck boost regulator works in hysteresis mode and

regulates the output voltage to a slightly higher value than the

target output voltage with switching pulses. When the output

voltage increases until the output sense signal exceeds the

hysteresis upper threshold, the regulator enters sleep mode. In

sleep mode, the high-side and low-side MOSFET and a majority

of the control circuitry are disabled to allow a low quiescent

current as well as high efficiency performance. During sleep

mode, the output capacitor supplies the energy into the load,

the output voltage decreases until the voltage falls lower than

the hysteresis comparator lower threshold, and the regulator

wakes up and generates the switching pulses to charge the

output again.

Program Output Voltages

The ADP5360 buck boost regulator provides output voltage

options from 1.8 V to 2.9 V with a 100 mV step, and 2.95 V

to 5.5 V with 50 mV step, which can be programmed by the

VOUT_BUCKBST[5:0] bits, Address 0x2C, and set via the I2C

interface (see Table 62). The buck boost regulator also provides

a fixed output voltage programmed via the factory fuse.

For the output voltage settings, the feedback resistor divider is

built in the ADP5360. An ultra low power voltage reference and

an integrated high impedance (50 MΩ typical) feedback divider

network contribute to the low quiescent current.

Enable and Disable

The ADP5360 includes a hardware enable pin (EN2). A logic

high in the EN2 pin starts the buck boost regulator. Because of the

low quiescent current design, it is typical for the regulator to start

switching after a delay of a few milliseconds from when the

EN2 pin pulls high. To avoid unexpected leakage current, do

not pull the EN pin high to the ISOB pin. However, do pull the

EN2 pin high to the VSYS pin with the resistor.

The I2C register bit, EN_BUCKBST, Address 0x2B, can also

control the buck boost enable and disable, which are logically

OR’ed with the EN2 pin. For example, set the EN_BUCKBST bit

to low, then use the hardware EN2 pin to control the buck boost

enable and disable, or pull the EN2 pin low, and then set the

EN_BUCKBST bit using the I2C inteface.

ADP5360ACBZ-1-R7 Datasheet(PDF) 30 Page - Analog Devices

ADP5360ACBZ-1-R7 Datasheet(HTML) 30 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL