ADP5360

Data Sheet

Rev. 0 | Page 8 of 60

Table 5.

Parameter

Symbol

Min

Typ

Max

Unit

Capacitive Load, Each Bus Line

400

pF

SCL Clock Frequency

400

kHz

SCL High Time

0.6

µs

SCL Low Time

1.3

µs

Data Setup Time

100

ns

0

0.9

µs

Setup Time for Repeated Start

0.6

µs

Hold Time for Start and Repeated Start

0.6

µs

Bus Free Time Between a Stop Condition and a Start Condition

1.3

µs

Setup Time for Stop Condition

0.6

µs

Rise Time of SCL and SDA

20

300

ns

Fall Time of SCL and SDA

20

300

ns

Pulse Width of Suppressed Spike

0

50

ns

1

A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. See Figure 2 for more information.

Timing Diagram

S = START CONDITION

Sr = REPEATED START CONDITION

P = STOP CONDITION

S

Sr

P

S

SDA

SCL

RECOMMENDED INPUT AND OUTPUT CAPACITANCE AND INDUCTANCE

Table 6.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CAPACITANCE

Effective capacitance

VBUS Capacitance

1.0

2.2

µF

VDD Pin Capacitance

0.47

1.0

10

μF

Total Capacitance

VSYS Pin

4.7

10

µF

ISOB Pin

4.7

10

µF

VIN1 Pin

2.2

10

µF

VIN2 Pin

2.2

10

µF

VOUT1 Node

1

10

µF

VOUT2 Pin

1

10

µF

INDUCTANCE

Buck

2.2

4.7

6.8

µH

Buck Boost

2.2

4.7

6.8

µH