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ADP5360ACBZ-1-R7 Datasheet(PDF) 52 Page - Analog Devices

Part # ADP5360ACBZ-1-R7
Description  Advanced Battery Management PMIC with Ultra Low Power Buck and Buck Boost
PDF  60 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADP5360ACBZ-1-R7 Datasheet(HTML) 52 Page - Analog Devices

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ADP5360
Data Sheet
Rev. 0 | Page 52 of 60
Table 67. PGOOD2_MASK Register, Address 0x31 Bit Descriptions
Bit(s) Bit Name
Access Default
Description
7
PG2_REV
R/W
0
This bit configures the active low output of the PGOOD2 pin output.
0 = disable active low.
1 = enable active low.
[6:5]
Reserved
Not applicable
Reserved
.
4
CHGCMPLT_MASK2
R/W
0
This bit configures the external PGOOD2 pin.
0 = does not send the output charger complete signal to the external PGOOD2 pin.
1 = sends the output charger complete signal to the external PGOOD2 pin.
3
VBUSOK_MASK2
R/W
0
This bit configures the external PGOOD2 pin.
0 = does not send the output VBUS voltage status signal to the external
PGOOD2 pin.
1 = sends the output VBUS voltage status signal to the external PGOOD2 pin.
2
BATOK_MASK2
R/W
0
This bit configures the external PGOOD2 pin.
0 = does not send the output battery voltage okay signal to the external
PGOOD2 pin.
1 = sends the output battery voltage okay signal to the external PGOOD2 pin.
1
VOUT2OK_MASK2
R/W
0
This bit configures the external PGOOD2 pin for buck boost output.
0 = does not send the output buck boost PGOOD signal to the external PGOOD2 pin.
1 = sends the output buck boost PGOOD signal to the external PGOOD2 pin.
0
VOUT1OK_MASK2
R/W
0
This bit configures the external PGOOD2 pin. This bit is not effective if the buck
is configured in load switch mode.
0 = does not send the output buck PGOOD signal to the external PGOOD2 pin.
1 = sends the output buck PGOOD signal to the external PGOOD2 pin.
Table 68. INTERRUPT_ENABLE1 Register, Address 0x32 Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
7
EN_SOCLOW_INT
R/W
0
When high, the battery low state of the charge interrupt is allowed.
6
EN_SOCACM_INT
R/W
0
When high, the state of e tcharge accumulation interrupt is allowed.
5
EN_ADPICHG_INT
R/W
0
When high, the VBUS adaptive charge current-limit interrupt is allowed.
4
EN_BATPRO_INT
R/W
0
When high, the battery protection interrupt is allowed.
3
EN_THR_INT
R/W
0
When high, the THR temperature threshold interrupt is allowed.
2
EN_BAT_INT
R/W
0
When high, the battery voltage threshold interrupt is allowed.
1
EN_CHG_INT
R/W
0
When high, the charger mode change interrupt is allowed.
0
EN_VBUS_INT
R/W
0
When high, the VBUS pin voltage threshold interrupt is allowed.
Table 69. INTERRUPT_ENABLE2 Register, Address 0x33 Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
7
EN_MR_INT
R/W
0
When high, the MR press interrupt is allowed.
6
EN_WD_INT
R/W
0
When high, the watchdog alarm interrupt is allowed.
5
EN_BUCKPG_INT
R/W
0
When high, the VOUT1OK change interrupt is allowed.
4
EN_BUCKBSTPG_INT
R/W
0
When high, the VOUT2OK change interrupt is allowed.
[3:0]
Reserved
R/W
Not applicable
Reserved
.



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