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MMPF0200Z Datasheet(PDF) 22 Page - NXP Semiconductors

Part # MMPF0200Z
Description  12 Channel Configurable Power Management Integrated Circuit
PDF  118 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MMPF0200Z Datasheet(HTML) 22 Page - NXP Semiconductors

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Analog Integrated Circuit Device Data
22
Freescale Semiconductor
PF0200Z
Functional Block Requirements and Behaviors
Start-up
6.1.2.1
Start-up Sequence and Timing
Each regulator has 5-bits allocated to program its start-up time slot from a turn on event; therefore, each can be placed from
position one to thirty-one in the start-up sequence. The all zeros code indicates that a regulator is not part of the start-up
sequence and will remain off. See Table 10. The delay between each position is equal; however, four delay options are available.
See Table 11. The start-up sequence will terminate at the last programmed regulator.
6.1.2.2
PWRON Pin Configuration
The PWRON pin can be configured as either a level sensitive input (PWRON_CFG = 0), or as an edge sensitive input
(PWRON_CFG = 1). As a level sensitive input, an active high signal turns on the part and an active low signal turns off the part,
or puts it into Sleep mode. As an edge sensitive input, such as when connected to a mechanical switch, a falling edge will turn
on the part and if the switch is held low for greater than or equal to 4.0 seconds, the part will turn off or enter Sleep mode.
6.1.2.3
I2C Address Configuration
The I2C device address can be programmed from 0x08 to 0x0F. This allows flexibility to change the I2C address to avoid bus
conflicts. Address bit, I2C_SLV_ADDR[3] in OTP_I2C_ADDR register is hard coded to “1” while the lower three LSBs of the I2C
address (I2C_SLV_ADDR[2:0]) are programmable as shown in Table 13.
Table 10. Start-up Sequence
SWxx_SEQ[4:0]/
VGENx_SEQ[4:0]/
VREFDDR_SEQ[4:0]
Sequence
00000
Off
00001
SEQ_CLK_SPEED[1:0] * 1
00010
SEQ_CLK_SPEED[1:0] * 2
**
**
**
**
11111
SEQ_CLK_SPEED[1:0] * 31
Table 11. Start-up Sequence Clock Speed
SEQ_CLK_SPEED[1:0]
Time (
s)
00
500
01
1000
10
2000
11
4000
Table 12. PWRON Configuration
PWRON_CFG
Mode
0
PWRON pin HIGH = ON
PWRON pin LOW = OFF or Sleep mode
1
PWRON pin pulled LOW momentarily = ON
PWRON pin LOW for 4.0 seconds = OFF or Sleep mode



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