MMPF0200Z datasheet(37/118 Pages) NXP

37 / 118 page

Analog Integrated Circuit Device Data



Freescale Semiconductor

PF0200Z

Functional Block Requirements and Behaviors

Power Generation

3. Sleep Mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest

state retention voltage of a given processor; it is selected by I2C bits SW1ABOFF[5:0] for SW1A/B and by bits

SWxOFF[6:0] for SW2, and SW3A/B. Voltage transitions initiated by a turn-off event are governed by the

SW1ABDVSSPEED[1:0] and SWxDVSSPEED[1:0] I2C bits shown in Table 32 and Table 33, respectively.

Table 30, Table 31, Table 32, and Table 33 summarize the set point control and DVS time stepping applied to all regulators.

The regulators have a strong sourcing capability and sinking capability in PWM mode, therefore the fastest rising and falling

slopes are determined by the regulator in PWM mode. However, if the regulators are programmed in PFM or APS mode during

a DVS transition, the falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced,

controlled DVS transitions in PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode

operation.

The following diagram shows the general behavior for the regulators when initiated with I2C programming, or standby control.

During the DVS period the overcurrent condition on the regulator should be masked.

Table 30. DVS Control Logic for SW1A/B

STANDBY

Set Point Selected by

SW1AB[5:0]

SW1ABSTBY[5:0]

Table 31. DVS Control Logic for SW2 and SW3A/B

STANDBY

Set Point Selected by

SWx[6:0]

SWxSTBY[6:0]

Table 32. DVS Speed Selection for SW1A/B

SW1ABDVSSPEED[1:0]

Function

25 mV step each 2.0

s

01 (default)

25 mV step each 4.0

s

25 mV step each 8.0

s

25 mV step each 16

s

Table 33. DVS Speed Selection for SW2 and SW3A/B

SWxDVSSPEED[1:0]

Function

SWx[6] = 0 or SWxSTBY[6] = 0

Function

SWx[6] = 1 or SWxSTBY[6] = 1

25 mV step each 2.0

s

50 mV step each 4.0

s

01 (default)

25 mV step each 4.0

s

50 mV step each 8.0

s

25 mV step each 8.0

s

50 mV step each 16

s

25 mV step each 16

s

50 mV step each 32

s

MMPF0200Z Datasheet(PDF) 37 Page - NXP Semiconductors

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