MCF5373CAB180 datasheet(22/46 Pages) NXP

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MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4

Electrical Characteristics

Freescale Semiconductor

Figure 9. SDR Write Timing

SD9

SD_DQS[3:2] input hold relative to SD_CLK7

tDQISDCH Does not apply. 0.5×SD_CLK fixed width.

SD10

Data (D[31:0]) Input Setup relative to SD_CLK (reference

only)8

tDVSDCH

0.25

SD_CLK

—ns

SD11

Data Input Hold relative to SD_CLK (reference only)

tDISDCH

1.0

—

SD12

Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid

tSDCHDMV

—

0.75

× SD_CLK

+ 0.5

SD13

Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold

tSDCHDMI

1.5

—

1 The FlexBus and SDRAM clock operates at the same frequency of the internal bus clock. See the PLL chapter of the MCF5373

Reference Manual for more information on setting the SDRAM clock rate.

2 SD_CLK is one SDRAM clock in (ns).

3 Pulse width high plus pulse width low cannot exceed min and max clock period.

4 Pulse width high plus pulse width low cannot exceed min and max clock period.

5 SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation

from this guideline is expected. SD_DQS only pulses during a read cycle and one pulse occurs for each data beat.

6 SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle

variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat.

7 The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge

does not affect the memory controller.

8 Because a read cycle in SDR mode uses the DQS circuit within the device, it is most critical that the data valid window be

centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup

spec is provided as guidance.

Table 10. SDR Timing Specifications (continued)

Symbol

Characteristic

Symbol

Min

Max

Unit

SD_CLK

SDDM

D[31:0]

A[23:0]

SD_BA[1:0]

CMD

ROW

SD1

SD4

COL

SD5

WD1

WD2

WD3

WD4

SD12

SD11

SD_CSn

SD_RAS

SD_WE

SD_CAS

SD2

SD3

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