Electrical Characteristics

Freescale Semiconductor

28

5.10

USB On-The-Go

The MCF5373 device is compliant with industry standard USB 2.0 specification.

5.11

SSI Timing Specifications

This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given

for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync

(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings

remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.

Num

Description

Symbol

Min

Max

Units

S1

(SYSCLK).

8

× t

SYS

—ns

S2

SSI_MCLK pulse width high / low

45%

55%

S3

minimum divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure

8

× t

SYS

—ns

S4

SSI_BCLK pulse width

45%

55%

S5

SSI_BCLK to SSI_FS output valid

—

15

ns

S6

SSI_BCLK to SSI_FS output invalid

-2

—

ns

S7

SSI_BCLK to SSI_TXD valid

—

15

ns

S8

SSI_BCLK to SSI_TXD invalid / high impedence

-4

—

ns

S9

SSI_RXD / SSI_FS input setup before SSI_BCLK

15

—

ns

S10

SSI_RXD / SSI_FS input hold after SSI_BCLK

0

—

ns

Num

Description

Symbol

Min

Max

Units

S11

SSI_BCLK cycle time

8

× t

SYS

—ns

S12

SSI_BCLK pulse width high/low

45%

55%

S13

SSI_FS input setup before SSI_BCLK

10

—

ns

S14

SSI_FS input hold after SSI_BCLK

3

—

ns

S15

SSI_BCLK to SSI_TXD/SSI_FS output valid

—

15

ns

S16

SSI_BCLK to SSI_TXD/SSI_FS output invalid/high

impedence

-2

—

ns

S17

SSI_RXD setup before SSI_BCLK

10

—

ns

S18

SSI_RXD hold after SSI_BCLK

3

—

ns