MCF5373CAB180 datasheet(11/46 Pages) NXP

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Pin Assignments and Reset States

MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor

NOTE

Test

TEST8

—

EVDD

124

E10

Power Supplies

EVDD

—

9, 69, 71, 81, 94,

103, 139, 160

E6, E7, F5–F7,

G5, H10, J8,

K8–K9

IVDD

—

36, 79, 97, 125,

156

E5, J9, K5, K10

PLL_VDD

—

J10

SD_VDD

—

11, 39, 41, 67,

105, 121, 137

E8–E9, F8–F10,

J4–J7, H5, K6,

USB_VDD

—

H12

VSS

—

10, 42, 68, 82,

89, 104, 122,

138, 159

G6–G9, H6–H9

PLL_VSS

—

H11

USB_VSS

—

J14

1 Refers to pin’s primary function.

2 Pull-up enabled internally on this signal for this mode.

3 The SDRAM functions of these signals are not programmable by the user. They are dynamically switched by the processor

when accessing SDRAM memory space and are included here for completeness.

4 Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating the

DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.

5 GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate

functions.

6 MCF53721 only.

7 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning

these pins.

8 Pull-down enabled internally on this signal for this mode.

Table 3. MCF5372/3 Signal Information and Muxing (continued)

Signal Name

GPIO

Alternate 1

Alternate 2

MCF5372

MCF5373

160 QFP

MCF5372L

MCF53721

MCF5373L

196 MAPBGA

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