MCF5373CAB180 datasheet(30/46 Pages) NXP

30 / 46 page

MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4

Electrical Characteristics

Freescale Semiconductor

Table 17 lists specifications for the I2C output timing parameters shown in Figure 17.

Figure 17 shows timing for the values in Table 17 and Table 16.

Figure 17. I2C Input/Output Timings

I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL =0.5 V)

—

Clock high time

—

tcyc

Data setup time

—

Start condition setup time (for repeated start condition only)

—

tcyc

Stop condition setup time

—

tcyc

Table 17. I2C Output Timing Specifications between SCL and SDA

Num

Characteristic

Min

Max

Units

I11

1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum

frequency (IFDR = 0x20) results in minimum output timings as shown in Table 17. The I2C interface is

designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual

position is affected by the prescale and division values programmed into the IFDR; however, the numbers

given in Table 17 are minimum values.

Start condition hold time

—

tcyc

I2 1

Clock low period

—

tcyc

I3 2

2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive

low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and

pull-up resistor values.

I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH =2.4 V)

—

µs

I4 1

Data hold time

—

tcyc

I5 3

3 Specified at a nominal 50-pF load.

I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)

—

I6 1

Clock high time

—

tcyc

I7 1

Data setup time

—

tcyc

I8 1

Start condition setup time (for repeated start condition only)

—

tcyc

I9 1

Stop condition setup time

—

tcyc

Table 16. I2C Input Timing Specifications between SCL and SDA (continued)

Num

Characteristic

Min

Max

Units

I2C_SCL

I2C_SDA

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