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ES9038Q2M Datasheet(PDF) 4 Page - ESS Technology,Inc |
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ES9038Q2M Datasheet(HTML) 4 Page - ESS Technology,Inc |
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4 / 65 page  CONFIDENTIAL Rev. 1.3 July 17, 2019 ES9038Q2M Datasheet ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643- 8800 • Fax (408) 643-8801 4 ES9038Q2M PIN DESCRIPTIONS Pin Name Pin Type Reset State Pin Description 1 AVCC_R Power Power DAC analog output stage reference supply for the Right Channel 2 DACRB AO Ground Differential Negative Output for the Right Channel 3 DACR AO Ground Differential Positive Output for the Right Channel 4 BIAS O 1’b0 General Output. Controlled by software. See Register 45: Low Power and Auto Calibration for more information. 5 SW I/O GPIO2 / Tri-stated General Output • Can be used with switch input of SABRE9602. See Register 39: General Configuration 2 for more information. In reset state, a 120k ohm resistor connects between SW and GPIO2. 6 FSYNC O Tri-stated General Output with output clock options. • Can be used with FSYNC of SABRE9602 to set its charge pump frequency. See Register 30-31: Charge Pump Clock for more information 7 HPSDb O 1’b0 General Output. Can be used for Headphone Shutdown of SABRE9602 Grounded through 100k ohm resistor in reset state. 8 DACL AO Ground Differential Positive Output for the Left Channel 9 DACLB AO Ground Differential Negative Output for the Left Channel 10 AVCC_L Power Power DAC analog output stage reference supply for the Left Channel 11 AGND_L Ground Ground DAC analog output stage ground for the Left Channel 12 VCCA Power Power Analog +3.3V for OSC 13 DVCC Power Power Digital +1.8V to +3.3V 14 DGND Ground Ground Digital Ground 15 DVDD Power Power Digital Core Voltage, nominally +1.2V, supplied by an internal regulator from DVCC. 16 GPIO2 I/O Tri-stated / SW General purpose input/output pin 2, or SPDIF Input 5 • In reset state, a 120k ohm resistor connects between SW and GPIO2 allowing GPIO2 to switch input of SABRE9602. See Register 39: General Configuration 2 for more information. 17 GPIO1 I/O Tri-stated General purpose input/output pin 1, or SPDIF Input 4. 18 DATA2 I Tri-stated DSD Data2 (R) or PCM Data CH1/CH2 or SPDIF Input 2 19 DATA1 I/O Tri-stated Master mode off or non-PCM mode • Input for DSD Data1 (L) or PCM Frame Clock or SPDIF Input 3 Master mode on and PCM mode • Output for PCM Frame Clock 20 DATA_CLK I/O Tri-stated Master mode off • Input for PCM Bit Clock or DSD Bit Clock or SPDIF Input 1 Master mode on • Output for PCM or DSD Bit Clock 21 RESETB I Ground Master Reset / Power Down (active low) 22 RT1 - Tri-stated Reserved, must be connected to DGND. 23 SCL I Tri-stated I2C Clock Input 24 SDA I/O Tri-stated I2C Serial Data Input/Output 25 ADDR I Tri-stated I2C Address Select |
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