ES9038Q2M datasheet(40/65 Pages) ESS

40 / 65 page

CONFIDENTIAL Rev. 1.3

July 17, 2019

ES9038Q2M Datasheet

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-

8800 • Fax (408) 643-8801

Bits

[7]

[6]

[5:4]

[3]

[2]

[1]

[0]

Mnemonic

reserved

adc_order

adc_clk

reserved

adc_ditherb

reserved

adc_pdb

Default

1’b0

2’b00

1’b0

Bit

Mnemonic

Description

[7]

reserved

[6]

adc_order

Selects whether the ADC uses a first order modulator or a second order

modulator in the analog section.

•

1’b0: uses a first order modulator providing the best performance

(default)

•

1’b1: uses a second order modulator (recommended for better

performance)

[5:4]

adc_clk

Sets the clock dividing ratio for the ADC analog section. This also

affects the decimation filter stages.

•

2’d0: ADC_CLK = CLK

•

2’d1: ADC_CLK = CLK/2

•

2’d2: ADC_CLK = CLK/4

•

2’d3: ADC_CLK = CLK/8

[3]

reserved

[2]

adc_ditherb

Allows the ADC dither to be disabled on a per ADC basis.

•

1’b0: uses TPDF shaped dither providing the best performance

(default)

•

1’b1: disabled dither

[1]

reserved

[0]

adc_pdb

Shuts down the ADC. Note: GPIO must be configured as ADC input for

the ADC to function correctly.

•

1’b0: shuts down the ADC (default)

•

1’b1: enables the ADC analog stage

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