ES9038Q2M datasheet(14/65 Pages) ESS

14 / 65 page

CONFIDENTIAL Rev. 1.3

July 17, 2019

ES9038Q2M Datasheet

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-

8800 • Fax (408) 643-8801

Serial Control Interface

The registers inside the chip are programmed via an I2C interface. The diagram below shows the timing for this interface.

The chip address can be set to 2 different settings via the ADDR pin.

ADDR

CHIP ADDRESS

0x90

0x92

Note:

•

Multi-byte reads are not supported and may cause the I2C decoder to become unresponsive until a reset occurs.

I2C Timing Table

Start

Stop

Parameter

Symbol

MCLK

Constraint

Standard-Mode

Fast-Mode

Unit

MIN

MAX

MIN

MAX

SCL Clock Frequency

fSCL

< MCLK/20

100

400

kHz

START condition hold time

tHD,STA

4.0

0.6

s

LOW period of SCL

tLOW

>10/MCLK

4.7

1.3

s

HIGH period of SCL (>10/MCLK)

tHIGH

>10/MCLK

4.0

0.6

s

START condition setup time (repeat)

tSU,STA

4.7

0.6

s

SDA hold time from SCL falling

All except NACK read

NACK read only

tHD,DAT

2/MCLK

s

SDA setup time from SCL rising

tSU,DAT

250

100

Rise time of SDA and SCL

1000

300

Fall time of SDA and SCL

300

STOP condition setup time

tSU,STO

0.6

s

Bus free time between transmissions

tBUF

4.7

1.3

s

Capacitive load for each bus line

400

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