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ES9038Q2M Datasheet(PDF) 6 Page - ESS Technology,Inc

Part # ES9038Q2M
Description  32-Bit Stereo Low Power Audio DAC
PDF  65 Pages
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Manufacturer  ESS [ESS Technology,Inc]
Direct Link  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9038Q2M Datasheet(HTML) 6 Page - ESS Technology,Inc

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CONFIDENTIAL Rev. 1.3
July 17, 2019
ES9038Q2M Datasheet
ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-
8800 • Fax (408) 643-8801
6
System Clock and Audio Inputs
Sampling Rate Notations
Mode
FSR
raw sample rate at
audio interface
fs
sample rate for filter
specification
DSD
DATA_CLK
FSR / 64
DoP
Frame Clock Rate
FSR / 4
Serial (PCM) Normal Mode
Frame Clock Rate
FSR
Serial (PCM) OSF Bypass Mode
Frame Clock Rate
FSR / 8
SPDIF
SPDIF Audio Rate
FSR
System Clock (XI) and Audio Master Clock (MCLK)
The system clock (XI) can be generated with a crystal using the built-in oscillator or supplied externally.
o
The maximum XI frequency is 100MHz as specified in ANALOG PERFORMANCE and XI Timing.
o
The audio master clock (MCLK) is divided down from XI via clk_gear in Register 0: System Registers.
o
The minimum MCLK frequency for a given raw sample rate FSR is specified in ANALOG PERFORMANCE.
o
The minimum MCLK frequency for a given I2C clock is specified in the table under I2C Timing Table.
PCM Pin Connections
Pin Name
Description
DATA1
Frame clock
DATA2
2-channel PCM serial data
DATA_CLK
Bit clock for PCM audio format
Note: DATA_CLK frequency must be (2 x serial_length) x FSR.
serial_length can be set in Register 1: Input selection.
SPDIF Pin Connections
Pin Name
Description
GPIO2~1
SPDIF input 5~4
DATA2~1
SPDIF input 3~2
DATA_CLK
SPDIF input 1
An SPDIF source multiplexer allows for up to 5 SPDIF sources to be connected to the data and GPIO pins selectable via
Register 11: SPDIF Select . SPDIF input mode can be manually selected by input_select in Register 1: Input selection or
automatically selected if auto_select in Register 1: Input selection is set to a mode allowing automatic SPDIF selection.
DSD Pin Connections
Pin Name
Description
DATA2~1
2-channel DSD data input
DATA_CLK
Bit clock for DSD data input
Note: DATA_CLK frequency must be FSR.



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