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SPC572LX Datasheet(PDF) 9 Page - STMicroelectronics |
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SPC572LX Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 112 page  DocID027866 Rev 5 9/112 SPC572Lx Introduction 111 Figure 1. Block diagram Nexus 3 VLE Scalar SP-FPU BIU LFAST support) SPU JTAGM JTAGC INTC_2 SWT_3 SWT_2 STM_2 e200z215An3–80 MHz Core Ethernet (LFAST & SIPI) DMA CH MUX 16ch eDMA 40 MHz Concentrator 40 MHz M2 M0 M1 Cross Bar Switch (AMBA 2.0 v6 AHB)–80 MHz System Memory Protection Unit (SMPU) 32 ADD 32 DATA Load/Store 32 ADD 32 DATA Instruction 32 ADD 32 DATA Peripheral Bridge 40 MHz Decorated Storage SRAM Control Decorated Access Flash Controller 8 x 128 32 ADD 32 DATA S2 S1 S0 32 ADD 32 DATA 32 ADD 32 DATA Overlay Backdoor for system RAM SRAM 64 KB NAR Overlay/Trace RAM 8 KB 128-bit Page Line 1.5 MB flash 6 x 256 KB code flash 2 x 16 KB data EEPROM NVM Peripheral Cluster Mini Cache allocation diagram) (see Periphery 32 ADD 32 DATA 32 ADD 32 DATA DCI (without Zipwire |
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