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SPC572LX Datasheet(PDF) 30 Page - STMicroelectronics |
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SPC572LX Datasheet(HTML) 30 Page - STMicroelectronics |
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30 / 112 page ![]() Electrical characteristics SPC572Lx 30/112 DocID027866 Rev 5 Table 15. MEDIUM configuration output buffer electrical characteristics Symbol C Parameter Conditions(1) Value(2) Unit Min Typ Max ROH_M CC P PMOS output impedance MEDIUM configuration 4.5 V < VDD_HV_IO < 5.5 V Push pull, IOH < 2 mA 120 200 260 Ω ROL_M CC P NMOS output impedance MEDIUM configuration 4.5 V < VDD_HV_IO < 5.5 V Push pull, IOL < 2 mA 120 200 260 Ω fMAX_M CC T Output frequency MEDIUM configuration CL =25 pF(3) —— 12 MHz CL =50 pF(3) —— 6 DCL = 200 pF(3) —— 1.5 tTR_M CC T Transition time output pin MEDIUM configuration(4) CL = 25 pF 4.5 V < VDD_HV_IO < 5.5 V 10 — 30 ns CL =50 pF 4.5 V < VDD_HV_IO < 5.5 V 20 — 60 DCL = 200 pF 4.5 V < VDD_HV_IO < 5.5 V 60 — 200 CL = 25 pF, 3.0 V < VDD_HV_IO < 3.6 V(5) 12 — 42 CL = 50 pF, 3.0 V < VDD_HV_IO < 3.6 V(5) 24 — 86 CL = 200 pF, 3.0 V < VDD_HV_IO < 3.6 V(5) 70 — 300 |tSKEW_M| CC T Difference between rise and fall time —— — 25 % IDCMAX_M CC D Maximum DC current — — — 4 mA TPHL/PLH CC D Propagation delay CL = 25 pF, 4.5 V < VDD_HV_IO < 5.9 V — — 35 ns CL = 25 pF, 3.0 V < VDD_HV_IO < 3.6 V —— 42 CL = 50 pF, 4.5 V < VDD_HV_IO < 5.9 V —— 70 CL = 50 pF, 3.0 V < VDD_HV_IO < 3.6 V(5) —— 85 1. All VDD_HV_IO conditions for 4.5 V to 5.5 V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid for VSIO[VSIO_xx] = 0 2. All values need to be confirmed during device validation. 3. CL is the sum of external capacitance. Device and package capacitances (CIN, defined in Table 12) are to be added to calculate total signal capacitance (CTOT = CL + CIN). |
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