71M6545HT-IGTRSLASHF datasheet(30/66 Pages) MAXIM

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71M6545T/71M6545HT

Energy Meter ICs

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samples are polled by the hardware. If the sample indi-

cates a pending interrupt when the interrupt is enabled,

then the interrupt request flag is set. On the next instruc-

tion cycle, the interrupt is acknowledged by hardware

forcing an LCALL to the appropriate vector address, if the

following conditions are met:

• No interrupt of equal or higher priority is already in

progress.

• An instruction is currently being executed and is not

completed.

• The instruction in progress is not RETI or any write

access to the registers IEN0, IEN1, IEN2, IP0 or IP1.

The following SFR registers control the interrupt functions:

• The interrupt enable registers: IEN0, IEN1 and IEN2.

• The Timer/Counter control registers, TCON and

T2CON.

• The interrupt request register, IRCON.

• The interrupt priority registers: IP0 and IP1.

External MPU Interrupts

The seven external interrupts are the interrupts external

to the 80515 core, i.e., signals that originate in other

parts of the 71M654xT, for example the CE, DIO, RTC, or

EEPROM interface.

The polarity of interrupts 2 and 3 is programmable in

the MPU via the I3FR and I2FR bits in T2CON (SFR

0xC8). Interrupts 2 and 3 should be programmed for

falling sensitivity (I3FR = I2FR = 0). The generic 8051

MPU literature states that interrupts 4 through 6 are

defined as rising-edge sensitive. Thus, the hardware

signals attached to interrupts 5 and 6 are inverted to

achieve the edge polarity shown in Table 9.

External interrupt 0 and 1 can be mapped to pins on the

device using DIO resource maps.

On-Chip Resources

Flash Memory

The device includes 64KB of on-chip flash memory. The

flash memory primarily contains MPU and CE program

code. It also contains images of the CE RAM and I/O

RAM. On power-up, before enabling the CE, the MPU

copies these images to their respective locations.

Flash space allocated for the CE program is limited to

4096 16-bit words (8KB). The CE program must begin

on a 1KB boundary of the flash address space. The

CE_LCTN[5:0] field defines where in flash the CE code

resides. The address of the CE program is 0bXXXX XX00

0000 0000, where XXXX XX represents one of the 64

1KB pages at which the CE program begins.

Flash memory can be accessed by the MPU and the CE

for reading, and by the SPI interface for reading or writing.

MPU/CE RAM

The 71M6545T/HT includes 5KB of static RAM memory

on-chip (XRAM) plus 256 bytes of internal RAM in the

MPU core. The static RAM is used for data storage for

both MPU and CE operations.

I/O RAM

The I/O RAM can be seen as a series of hardware reg-

isters that control basic hardware functions. I/O RAM

address space starts at 0x2000.

The 71M6545T/HT includes 128 bytes NV RAM memory

on-chip in the I/O RAM address space (addresses 0x2800

to 0x287F). This memory section is supported by the volt-

age applied at VBAT_RTC and the data in it are preserved

in BRN, LCD, and SLP modes as long as the voltage at

VBAT_RTC is within specification.

Table 9. External MPU Interrupts

EXTERNAL

INTERRUPT

CONNECTION

POLARITY

FLAG

RESET

Digital I/O (IE0)

Programmable

Automatic

Digital I/O (IE1)

Programmable

Automatic

CE_PULSE (IE_XPULSE, IE_YPULSE, IE_WPLUSE, IE_VPULSE)

Rising

Manual

CE_BUSY (IE3)

Falling

Automatic

VSTAT (VSTAT[2:0] changed) (IE4)

Rising

Automatic

EEPROM busy (falling), SPI (rising) (IE_EEX, IE_SPI)

—

Manual

XFER_BUSY (falling), RTC_1SEC, RTC_1MIN, RTC_T, TC_TEMP

(IE_XFER, IE_RTC1S, IE_RTC1M, IE_RTCT)

Falling

Manual

71M6545HT-IGTR/F Datasheet(PDF) 30 Page - Maxim Integrated Products

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