SH79F3283PSLASH032PR datasheet(79/144 Pages) SINOWEALTH

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SH79F3283

Table 8.9 LED Control Register 1

ADH, Bank0

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

DISPCON1

MODSW

DUTY2

DUTY1

R/W

Reset Value

(POR/WDT/LVR/PIN)

Bit Number

Bit Mnemonic

Description

6-5

DUTY0

DUTY[2:1]

LED duty selection bit (Combination control with DUTY0)

000: 1/4 duty

001: 1/8 duty

010: 1/3 duty

011: 1/5 duty

100: 1/6 duty

101: 1/7 duty

others: 1/4 duty

MODSW

LCD/LED shared control bit

0: P0SS is valid

1: all the LCD/LED Pins worked as IO

Note: When MODSW = 1, set OP_MODSW to keep LCD counter data or not.

When OP_MODSW = 0, the LCD counter data scan continue, when

OP_MODSW = 1, the LCD counter data scan stop, keep the data, continue

scan when MODSW = 0.

Table 8.10 LED Clock Control Register

ACH, Bank0

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

DISPCLK0

DCK0.1

DCK0.0

R/W

Reset Value

(POR/WDT/LVR/PIN)

Bit Number

Bit Mnemonic

Description

1-0

DCK[1:0]

LED clock prescaler select bit

00: 1/4 prescaler

01: 1/3 prescaler

10: 1/2 prescaler

11: 1/1 prescaler

Note: this register is valid when LCD clock is 128K RC only.

Note:

(1) When OP_OSC[3:0] is 1010, 1011 or 1101, LCD clock source is 32.768kHz, DISPCLK0 register is invalid, LCD frame is

64Hz.

(2) When OP_OSC[3:0] is others, LCD clock source is 128kHz, set DCK[1:0] bits in DISPCLK0 register, select 1/4, 1/3, 1/2,

1/1, prescaler, so that the LCD frame is 256/4Hz, 256/3Hz, 256/2Hz, 256/1Hz.

SH79F3283P/032PR Datasheet(PDF) 79 Page - SINOWEALTH Electronic Ltd

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