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STA8090GA Datasheet(PDF) 15 Page - STMicroelectronics

Part # STA8090GA
Description  Automotive GPS/Galileo/GLONASS/BeiDou/QZSS receiver
PDF  32 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STA8090GA Datasheet(HTML) 15 Page - STMicroelectronics

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STA8090GA
General description
31
3.4
APB peripherals
3.4.1
CAN
The 2 CAN(a) cores perform communication according to the CAN protocol version 2.0 part
A and B. The bit rate can be programmed to values up to 1 MBit/s. For the connection to the
physical layer, additional transceiver hardware is required.
CAN consists of the CAN core, message RAM, message handler, control registers and
module. For communication on a CAN network, individual message objects are configured.
The message objects and identifier masks for acceptance filtering of received messages are
stored in the message RAM. All functions concerning the handling of messages are
implemented in the message handler. These functions include acceptance filtering, the
transfer of messages between the CAN core and the message RAM, and the handling of
transmission requests as well as the generation of the module interrupt.
The register set of the CAN can be accessed directly by the CPU through the module
interface. These registers are used to control/configure the CAN core and the message
handler and to access the message RAM.
CAN features
Supports CAN protocol version 2.0 part A and B
32 messages objects
Each message object has its own identifier mask
Maskable interrupt
Disabled automatic re-transmission mode for time triggered CAN applications
Programmable loop-back mode for self-test operation
Two 16-bit module interfaces to the AMBA APB bus from ARM
3.4.2
UART
The UARTx (x = 1|2) performs serial-to-parallel conversion on data asynchronously
received from a peripheral device on UARTx_RX pin, and parallel-to-serial conversion on
data written by CPU for transmission on UARTx_TX pin. The transmit and receive paths are
buffered with internal FIFO memories allowing up to 64 data byte for transmission, and 64
data byte with 4-bit status (break, frame, parity, and overrun) for receive.
a. Only for STA8090GA (see Figure 6: Ordering information scheme).



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