CS47L35 datasheet(201/300 Pages) CIRRUS

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DS1085F3

201

CS47L35

4.16 Clocking and Sample Rates

Table 4-96. FLL1 Register Map

Bit

Label

Default

Description

R369 (0x0171)

FLL1_Control_1

FLL1_

FREERUN

FLL1 Free-Running Mode Enable

0 = Disabled

1 = Enabled

The FLL feedback mechanism is halted in Free-Running FLL Mode, and the latest

integrator setting is maintained

FLL1_ENA

FLL1 Enable

0 = Disabled

1 = Enabled

This should be set as the final step of the FLL1 enable sequence, i.e., after the other

FLL fields have been configured.

R370 (0x0172)

FLL1_Control_2

FLL1_CTRL_

UPD

FLL1 Control Update

Write 1 to apply the FLL1_N and FLL1_THETA field settings.

(Only valid if FLL1_ENA = 1)

9:0

FLL1_N[9:0]

0x008

FLL1 Integer multiply for FREF

(LSB = 1)

If updated while the FLL is enabled, the new value is only effective when a 1 is written

to FLL1_CTRL_UPD.

R371 (0x0173)

FLL1_Control_3

15:0 FLL1_

THETA[15:0]

0x0018 FLL1 Fractional multiply for FREF. Sets the numerator (multiply) part of the FLL1_

THETA / FLL1_LAMBDA ratio.

Coded as LSB = 1.

If updated while the FLL is enabled, the new value is only effective when a 1 is written

to FLL1_CTRL_UPD.

R372 (0x0174)

FLL1_Control_4

15:0 FLL1_

LAMBDA[15:0]

0x007D FLL1 Fractional multiply for FREF

This field sets the denominator (dividing) part of the FLL1_THETA / FLL1_LAMBDA

ratio.

Coded as LSB = 1.

R373 (0x0175)

FLL1_Control_5

11:8 FLL1_

FRATIO[3:0]

0x0

FLL1 FVCO clock divider

0x0 = 1

0x1 = 2

0x2 = 3

0x3 = 4

…

0xF = 16

R374 (0x0176)

FLL1_Control_6

7:6

FLL1_REFCLK_

DIV[1:0]

FLL1 Clock Reference Divider

00 = 1

01 = 2

10 = 4

11 = 8

MCLK (or other input reference) must be divided down to

13.5 MHz.

3:0

FLL1_REFCLK_

SRC[3:0]

0000

FLL1 Clock source

0000 = MCLK1

0001 = MCLK2

0011 = SLIMCLK

1000 = AIF1BCLK

1001 = AIF2BCLK

1010 = AIF3BCLK

1100 = AIF1LRCLK

1101 = AIF2LRCLK

1110 = AIF3LRCLK

All other codes are reserved

R375 (0x0177)

FLL1_Loop_

Filter_Test_1

FLL1_FRC_

INTEG_UPD

Write 1 to apply the FLL1_FRC_INTEG_VAL setting.

(Only valid if FLL1_FREERUN = 1)

11:0 FLL1_FRC_

INTEG_

VAL[11:0]

0x281

FLL1 Forced Integrator Value

R376 (0x0178)

FLL1_NCO_Test_

FLL1_INTEG_

VALID

FLL1 Integrator Valid. Indicates whether FLL1_INTEG is valid

0 = Not valid

1 = Valid

11:0 FLL1_

INTEG[11:0]

0x000

FLL1 Integrator Value (Read-only). Indicates the current FLL1 integrator setting. Only

valid if FLL1_INTEG_VALID = 1.

R377 (0x0179)

FLL1_Control_7

5:2

FLL1_GAIN[3:0]

0000

FLL1 Gain

0000 = 1

0001 = 2

0010 = 4

0011 = 8

0100 = 16

0101 = 32

0110 = 64

0111 = 128

1000–1111 = 256

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