CS47L35 datasheet(202/300 Pages) CIRRUS

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202

DS1085F3

CS47L35

4.16 Clocking and Sample Rates

R378 (0x017A)

FLL1_Control_8

15:12 FLL1_PHASE_

GAIN[3:0]

0010

FLL1 Phase Gain

0000 = Reserved

0001 = Reserved

0010 = 4

0011 = 8

0100 = 16

0101 = 32

0110 = 64

0111 = 128

1000–1111 = 256

FLL1_PHASE_

ENA

FLL1 Phase Integrator Control

0 = Disabled

1 = Enabled

10:8 FLL1_CTRL_

RATE[2:0]

001

FLL1 Control Ratio

000 = 1

001 = 2

010 = 4

011 = 8

100 = 16

101 = 32

110 = 64

111 = 128

R383 (0x017F)

FLL1_

Synchroniser_1

FLL1_SYNC_

ENA

FLL1 Synchronizer Enable

0 = Disabled

1 = Enabled

This should be set as the final step of the FLL1 synchronizer enable sequence, i.e.,

after the other synchronizer fields have been configured.

R384 (0x0180)

FLL1_

Synchroniser_2

9:0

FLL1_SYNC_

N[9:0]

0x000

FLL1 Integer multiply for FSYNC

(LSB = 1)

R385 (0x0181)

FLL1_

Synchroniser_3

15:0 FLL1_SYNC_

THETA[15:0]

0x0000 FLL1 Fractional multiply for FSYNC

This field sets the numerator (multiply) part of the FLL1_SYNC_THETA / FLL1_

SYNC_LAMBDA ratio.

Coded as LSB = 1.

R386 (0x0182)

FLL1_

Synchroniser_4

15:0 FLL1_SYNC_

LAMBDA[15:0]

0x0000 FLL1 Fractional multiply for FSYNC

This field sets the denominator (dividing) part of the FLL1_SYNC_THETA / FLL1_

SYNC_LAMBDA ratio.

Coded as LSB = 1.

R387 (0x0183)

FLL1_

Synchroniser_5

10:8 FLL1_SYNC_

FRATIO[2:0]

000

FLL1 Synchronizer FVCO clock divider

000 = 1

001 = 2

010 = 4

011 = 8

1XX = 16

R388 (0x0184)

FLL1_

Synchroniser_6

7:6

FLL1_

SYNCCLK_

DIV[1:0]

FLL1 Synchronizer Clock Reference Divider

00 = 1

01 = 2

10 = 4

11 = 8

MCLK (or other input reference) must be divided down to

13.5 MHz.

3:0

FLL1_

SYNCCLK_SRC

0000

FLL1 Synchronizer Clock source

0000 = MCLK1

0001 = MCLK2

0011 = SLIMCLK

1000 = AIF1BCLK

1001 = AIF2BCLK

1010 = AIF3BCLK

1100 = AIF1LRCLK

1101 = AIF2LRCLK

1110 = AIF3LRCLK

All other codes are reserved

R389 (0x0185)

FLL1_

Synchroniser_7

5:2

FLL1_SYNC_

GAIN[3:0]

0000

FLL1 Synchronizer Gain

0000 = 1

0001 = 2

0010 = 4

0011 = 8

0100 = 16

0101 = 32

0110 = 64

0111 = 128

1000–1111 = 256

FLL1_SYNC_

DFSAT

FLL1 Synchronizer Bandwidth

0 = Wide bandwidth

1 = Narrow bandwidth

R391 (0x0187)

FLL1_Spread_

Spectrum

5:4

FLL1_SS_

AMPL[1:0]

FLL1 Spread Spectrum Amplitude. Controls the extent of the spread-spectrum

modulation.

00 = 0.7% (triangle), 0.7% (ZMFM, dither)

01 = 1.1% (triangle), 1.3% (ZMFM, dither)

10 = 2.3% (triangle), 2.6% (ZMFM, dither)

11 = 4.6% (triangle), 5.2% (ZMFM, dither)

3:2

FLL1_SS_

FREQ[1:0]

FLL1 Spread Spectrum Frequency. Controls the spread spectrum modulation

frequency in Triangle Mode.

00 = 439 kHz

01 = 878 kHz

10 = 1.17 MHz

11 = 1.76 MHz

1:0

FLL1_SS_

SEL[1:0]

FLL1 Spread Spectrum Select.

00 = Disabled

01 = Zero Mean Frequency (ZMFM)

10 = Triangle

11 = Dither

Table 4-96. FLL1 Register Map (Cont.)

Bit

Label

Default

Description

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