CS47L35 datasheet(203/300 Pages) CIRRUS

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DS1085F3

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CS47L35

4.16 Clocking and Sample Rates

4.16.9.10FLL Interrupts and GPIO Output

The CS47L35 provides an FLL lock signal, which indicates whether FLL lock has been achieved (i.e., the FLL is locked to

the input reference signal).

The FLL lock signal is an input to the interrupt control circuit and can be used to trigger an interrupt event; see Section 4.15.

Note that the interrupt signal is debounced, and requires clocking to be present in order to assert the respective interrupt;

either the 32-kHz clock, or the SYSCLK signal, must be enabled to trigger an interrupt from the FLL lock signal.

The FLL lock signal can be output directly on a GPIO pin as an external indication of the FLL status. See Section 4.14 to

configure a GPIO pin for these functions. (This GPIO output is not debounced, and does not require clocking to be

present.)

Clock output signals derived from the FLL can be output on a GPIO pin. See Section 4.14 to configure a GPIO pin for this

function.

The FLL clocking configuration is shown in Fig. 4-65.

4.16.9.11Example FLL Calculation

The following example illustrates how to derive the FLL1 register fields to generate an oscillator frequency (FVCO) of

294.912 MHz from a 12.000-MHz reference clock (FREF). This is suitable for generating SYSCLK at 98.304 MHz and/or

DSPCLK at 147.456 MHz.

Note that, for the purposes of this calculation, it is assumed that the synchronizer is disabled.

1. Set FLL1_REFCLK_DIV to generate FREF  13.5 MHz:

FLL1_REFCLK_DIV = 00 (divide by 1)

2. Calculate N.K as given by N.K = FVCO / (FLL1_FRATIO × 3 × FREF). Assume FLL1_FRATIO = 0x0 (divide by 1).

N.K = 294912000 / (1 × 3× 12000000) = 8.192

3. Confirm that the calculated value of N is less than 1024.

4. Determine FLL1_N from the integer portion of N.K:

FLL1_N = 8 (0x008)

5. Determine GCD(FLL), as given by GCD(FLL) = GCD(FLL1_FRATIO × FREF, FVCO /3):

GCD(FLL) = GCD(1 × 12000000, 294912000 / 3) = 96000

6. Determine FLL1_THETA, as given by FLL1_THETA = (FVCO / 3 – (FLL1_N × FLL1_FRATIO × FREF)) / GCD(FLL):

FLL1_THETA = ((294912000 / 3) – (8 × 1 × 12000000)) / 96000

FLL1_THETA = 24 (0x0018)

7. Determine FLL1_LAMBDA, as given by FLL1_LAMBDA = (FLL1_FRATIO x FREF) / GCD(FLL):

FLL1_LAMBDA = (1 × 12000000) / 96000

FLL1_LAMBDA = 125 (0x007D)

8. Determine FLL1_GAIN, FLL1_PHASE_GAIN, FLL1_PHASE_ENA, and FLL1_CTRL_RATE as specified in

Section 4.16.9.4:

FLL1_GAIN = 0x5

FLL1_PHASE_GAIN = 0x2

FLL1_PHASE_ENA = 1

FLL1_CTRL_RATE = 0x1

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