CS47L35 datasheet(237/300 Pages) CIRRUS

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DS1085F3

237

CS47L35

5.2 Resets Summary

Figure 5-12. External Accessory Detect Components

5.2 Resets Summary

Table 5-3 summarizes of the CS47L35 registers and other programmable memory under different reset conditions. The

associated events and conditions are listed as follows:

• A power-on reset occurs when AVDD or DBVDD1 is below its respective reset threshold. Note that DCVDD is also

required for initial start-up; subsequent interruption to DCVDD should only be permitted as part of a control

sequence for entering Sleep Mode.

• A hardware reset occurs when the RESET input is asserted (Logic 0).

• A software reset occurs when register R0 is written to.

• Sleep Mode is selected when DCVDD is removed. Note that the AVDD and DBVDD1 supplies must be present

throughout the Sleep Mode duration.

5.3 Output-Signal Drive-Strength Control

The CS47L35 supports configurable drive-strength control for the digital output pins. This can be used to assist

system-level integration and design considerations.

Table 5-3. Memory Reset Summary

Reset Type

Always-On Registers 1

1.See Section 4.13 for details of Sleep Mode and the always-on registers.

Other Registers

Control-Write Sequencer Memory DSP Firmware Memory

Power-on reset

Reset

Hardware reset

Reset

Software reset

Reset

Retained

Retained 2

2.To retain the DSP firmware memory contents during software reset, it must be ensured that DCVDD is held above its reset threshold.

Sleep Mode

Retained

Reset

The measured impedance is reported using the MICD_STS and MICD_LVL bits.

If no accessory or push button is detected, the MICD_STS bit is cleared.

If MICD_STS = 1, one of the MICD_LVL bits is set to indicate the measured

impedance.

The applicable MICD_LVL bit for each push-button is noted below.

Detection of the microphone alone (no push-buttons closed) is indicated in

MICD_LVL[8].

MICDET

AGND

MICBIAS

2.2 k

(±2%)

Microphone

Push-Buttons

Analog Input

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