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CS47L35 Datasheet(PDF) 240 Page - Cirrus Logic |
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CS47L35 Datasheet(HTML) 240 Page - Cirrus Logic |
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240 / 300 page  240 DS1085F3 CS47L35 5.4 Digital Audio Interface Clocking Configurations Fig. 5-13 shows AIF Master Mode operation, using MCLK as the clock reference. Figure 5-13. AIF Master Mode, Using MCLK as Reference Fig. 5-14 shows AIF Master Mode operation, using MCLK as the clock reference. In this example, the FLL is used to generate the system clock, with MCLK as the reference. Figure 5-14. AIF Master Mode, Using MCLK and FLL as Reference Oscillator Processor AIFnBCLK AIFnLRCLK AIFnRXDAT AIFnTXDAT SYSCLK SYSCLK_SRC AIFn (Master Mode) AIFnBCLK FLL1 SLIMCLK CS47L35 Oscillator Processor AIFnBCLK AIFnLRCLK AIFnRXDAT AIFnTXDAT FLL1_REFCLK_SRC FLL1 SYSCLK SYSCLK_SRC AIFn (Master Mode) AIFnBCLK SLIMCLK MCLK1 MCLK2 AIFnLRCLK AIFnBCLK SLIMCLK CS47L35 |
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