CS47L35 datasheet(239/300 Pages) CIRRUS

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DS1085F3

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CS47L35

5.4 Digital Audio Interface Clocking Configurations

The digital audio interfaces (AIF1–AIF3) can be configured in master or slave modes. In all applications, it is important that

the system clocking configuration is correctly designed. Incorrect clock configurations lead to audible clicks arising from

dropped or repeated audio samples; this is caused by the inherent tolerances of multiple asynchronous system clocks.

To ensure reliable clocking of the audio interface functions, the external interface clocks (e.g., BCLK, LRCLK) must be

derived from the same clock source as SYSCLK.

In AIF Master Mode, the external BCLK and LRCLK signals are generated by the CS47L35 and synchronization of these

signals with SYSCLK is ensured. In this case, clocking of the AIF is typically derived from the MCLK1 or MCLK2 inputs,

either directly or via the FLL circuit. Alternatively, an AIFn or SLIMbus interface can be used to provide the reference clock

to which the AIF master can be synchronized.

In AIF Slave Mode, the external BCLK and LRCLK signals are generated by another device, as inputs to the CS47L35. In

this case, the system clock (SYSCLK) must be generated from a source that is synchronized to the external BCLK and

LRCLK inputs.

In a typical Slave Mode application, the BCLK input is selected as the clock reference, using the FLL to perform frequency

shifting. The MCLK1 or MCLK2 inputs can also be used, but only if the selected clock is synchronized externally to the

BCLK and LRCLK inputs. The SLIMbus interface can also provide the clock reference, via the FLL, provided that the BCLK

and LRCLK signals are externally synchronized with the SLIMCLK input.

The valid AIF clocking configurations are listed in Table 5-5 for AIF Master and AIF Slave Modes.

In each case, the SYSCLK frequency must be a valid ratio to the LRCLK frequency; the supported clocking rates are

defined by the SYSCLK_FREQ and SAMPLE_RATE_n fields.

The valid AIF clocking configurations are shown in Fig. 5-13 to Fig. 5-19. Note that, where MCLK1 is shown as the clock

source, it is equally possible to select MCLK2 as the clock source.

R5915 (0x171B)

GPIO14_CTRL2

GP14_DRV_STR

AIF2RXDAT/GPIO14 output drive strength

0 = 4 mA

1 = 8 mA

R5917 (0x171D)

GPIO15_CTRL2

GP15_DRV_STR

AIF2LRCLK/GPIO15 output drive strength

0 = 4 mA

1 = 8 mA

R5919 (0x171F)

GPIO16_CTRL2

GP16_DRV_STR

MIF1SCLK/GPIO16 output drive strength

0 = 4 mA

1 = 8 mA

Table 5-5. AIF Clocking Configurations

AIF Mode

Clocking Configuration

AIF Master Mode

SYSCLK_SRC selects MCLK1 or MCLK2 as SYSCLK source.