CS47L35 datasheet(243/300 Pages) CIRRUS

243 / 300 page

DS1085F3

243

CS47L35

5.5 PCB Layout Considerations

Fig. 5-19 shows AIF Slave Mode operation, using a separate interface as the clock reference. In this example, the FLL is

used to generate the system clock, with SLIMCLK as the reference. For correct operation, the SLIMCLK input must be

fully synchronized to the other audio interfaces.

Figure 5-19. AIF Slave Mode, Using Another Interface as Reference

5.5 PCB Layout Considerations

Poor PCB layout degrades the performance and is a contributory factor in EMI, ground bounce, and resistive voltage

losses. All external components should be placed as close to the CS47L35 device as possible, with current loop areas

kept as small as possible.

6 Register Map

The CS47L35 control registers are listed in the following tables. Note that only the register addresses described here

should be accessed; writing to other addresses may result in undefined behavior. Register bits that are not documented

should not be changed from the default values.

The CS47L35 register map is defined in two regions:

• The codec register space (below 0x3000) is defined in 16-bit word format

• The DSP register space (from 0x3000 upwards) is defined in 32-bit word format

It is important to ensure that all control interface register operations use the applicable data word format, in accordance

with the applicable register addresses.

The 16-bit codec register space is described in Table 6-1.

AIFnBCLK

AIFnLRCLK

AIFnRXDAT

AIFnTXDAT

FLL1_REFCLK_SRC

FLL1

Processor

Synchronous

Clock Generator

AIFnBCLK

AIFnLRCLK

AIFnRXDAT

AIFnTXDAT

SLIMCLK

SLIMDAT

FRAMER_REF_GEAR

Processor

AIFn

(Slave Mode)

AIFn

(Slave Mode)

SLIMbus

Interface

Automatic

Divider

MCLK1

MCLK2

SYSCLK

SYSCLK_SRC

AIFnBCLK

SLIMCLK

MCLK1

MCLK2

CS47L35

CS47L35 Datasheet(PDF) 243 Page - Cirrus Logic

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