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CS47L35 Datasheet(PDF) 246 Page - Cirrus Logic

Part # CS47L35
Description  Smart Codec with Low-Power Audio DSP
PDF  300 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L35 Datasheet(HTML) 246 Page - Cirrus Logic

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246
DS1085F3
CS47L35
6 Register Map
R372
(174h)
FLL1_Control_4
FLL1_LAMBDA [15:0]
007Dh
R373
(175h)
FLL1_Control_5
00
00
FLL1_FRATIO [3:0]
0
0
000
000
0000h
R374
(176h)
FLL1_Control_6
00
000
000
FLL1_REFCLK_DIV
[1:0]
0
0
FLL1_REFCLK_SRC [3:0]
0000h
R375
(177h)
FLL1_Loop_Filter_Test_
1
FLL1_
FRC_
INTEG_
UPD
0
0
0
FLL1_FRC_INTEG_VAL [11:0]
0281h
R376
(178h)
FLL1_NCO_Test_0
FLL1_
INTEG_
VALID
0
0
0
FLL1_INTEG [11:0]
0000h
R377
(179h)
FLL1_Control_7
00
000
000
00
FLL1_GAIN [3:0]
0
0
0000h
R378
(17Ah)
FLL1_Control_8
FLL1_PHASE_GAIN[3:0]
FLL1_
PHASE_
ENA
FLL1_CTRL_RATE[2:0]
00
000
110
2906h
R383
(17Fh)
FLL1_Synchroniser_1
00
000
000
00
000
00
FLL1_
SYNC_
ENA
0000h
R384
(180h)
FLL1_Synchroniser_2
00
000
0
FLL1_SYNC_N [9:0]
0000h
R385
(181h)
FLL1_Synchroniser_3
FLL1_SYNC_THETA [15:0]
0000h
R386
(182h)
FLL1_Synchroniser_4
FLL1_SYNC_LAMBDA [15:0]
0000h
R387
(183h)
FLL1_Synchroniser_5
00
000
FLL1_SYNC_FRATIO [2:0]
00
000
000
0000h
R388
(184h)
FLL1_Synchroniser_6
00
000
000
FLL1_SYNCCLK_DIV
[1:0]
0
0
FLL1_SYNCCLK_SRC [3:0]
0000h
R389
(185h)
FLL1_Synchroniser_7
00
000
000
00
FLL1_SYNC_GAIN [3:0]
0
FLL1_
SYNC_
DFSAT
0001h
R391
(187h)
FLL1_Spread_Spectrum
0
0
0
0
0
0
0
0
0
0
FLL1_SS_AMPL [1:0] FLL1_SS_FREQ [1:0] FLL1_SS_SEL [1:0]
0000h
R392
(188h)
FLL1_GPIO_Clock
0
0
0
0
0
0
0
0
FLL1_GPCLK_DIV [6:0]
FLL1_
GPCLK_
ENA
000Ch
R512
(200h)
Mic_Charge_Pump_1
00
000
000
00
000
CP2_
DISCH
CP2_
BYPASS
CP2_ENA
0006h
R531
(213h)
LDO2_Control_1
00
000
LDO2_VSEL [5:0]
0
0
LDO2_
DISCH
00
03E4h
R536
(218h)
Mic_Bias_Ctrl_1
MICB1_
EXT_CAP
0
000
00
MICB1_LVL [3:0]
0
MICB1_
RATE
MICB1_
DISCH
MICB1_
BYPASS
MICB1_
ENA
00E6h
R537
(219h)
Mic_Bias_Ctrl_2
MICB2_
EXT_CAP
0
000
00
MICB2_LVL [3:0]
0
MICB2_
RATE
MICB2_
DISCH
MICB2_
BYPASS
MICB2_
ENA
00E6h
R540
(21Ch)
Mic_Bias_Ctrl_5
00
000
000
00
MICB1B_
DISCH
MICB1B_
ENA
00
MICB1A_
DISCH
MICB1A_
ENA
0022h
R542
(21Eh)
Mic_Bias_Ctrl_6
00
000
000
00
MICB2B_
DISCH
MICB2B_
ENA
00
MICB2A_
DISCH
MICB2A_
ENA
0022h
R620
(26Ch)
SPK_Watchdog_1
00
000
000
00
00
SPK_SHUTDOWN_TIMER_SEL [3:0]
0000h
R659
(293h)
Accessory_Detect_
Mode_1
0
0
ACCDET_
SRC
00
000
10
000
ACCDET_MODE [2:0]
0080h
R667
(29Bh)
Headphone_Detect_1
00
000
HP_IMPEDANCE_
RANGE [1:0]
0
0
0
0
HP_CLK_DIV [1:0]
HP_RATE [1:0]
HP_POLL
(M)
0000h
R668
(29Ch)
Headphone_Detect_2
HP_DONE
HP_LVL [14:0]
0000h
R669
(29Dh)
Headphone_Detect_3
00
000
0
HP_DACVAL [9:0]
0000h
R671
(29Fh)
Headphone_Detect_5
0
0
0
0
0
0
HP_DACVAL_DOWN [9:0]
0000h
R675
(2A3h)
Mic_Detect_1
MICD_BIAS_STARTTIME [3:0]
MICD_RATE [3:0]
0
MICD_BIAS_SRC [2:0]
0
0
MICD_
DBTIME
MICD_
ENA
1102h
R676
(2A4h)
Mic_Detect_2
00
000
000
MICD_LVL_SEL [7:0]
009Fh
R677
(2A5h)
Mic_Detect_3
00
000
MICD_LVL [8:0]
MICD_
VALID
MICD_STS
0000h
R683
(2ABh)
Mic_Detect_4
MICDET_ADCVAL_DIFF [7:0]
0
MICDET_ADCVAL [6:0]
0000h
R710
(2C6h)
Micd_Clamp_control
00
000
000
00
0
MICD_
CLAMP_
OVD
MICD_CLAMP_MODE [3:0]
0010h
R712
(2C8h)
GP_Switch_1
00
000
000
00
000
0
SW1_MODE [1:0]
0000h
R723
(2D3h)
Jack_detect_analogue
00
000
000
00
000
0
JD2_ENA JD1_ENA
0000h
R768
(300h)
Input_Enables
00
000
000
00
00
IN2L_ENA IN2R_ENA IN1L_ENA IN1R_ENA
0000h
Table 6-1. Register Map Definition—16-bit region (Cont.)
Register
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default



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