NRF9160-SICA-R7 datasheet(47/400 Pages) NORDIC

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Application core

The EasyDMA Array List can be implemented by using the data structure ArrayList_type as illustrated in

the code example below using a READER EasyDMA channel as an example:

#define BUFFER_SIZE 4

typedef struct ArrayList

{

uint8_t buffer[BUFFER_SIZE];

} ArrayList_type;

ArrayList_type ReaderList[3] __at__ 0x20000000;

MYPERIPHERAL->READER.MAXCNT = BUFFER_SIZE;

MYPERIPHERAL->READER.PTR = &ReaderList;

MYPERIPHERAL->READER.LIST = MYPERIPHERAL_READER_LIST_ArrayList;

The data structure only includes a buffer with size equal to the size of READER.MAXCNT register. EasyDMA

uses the READER.MAXCNT register to determine when the buffer is full.

buffer[0]

buffer[1]

buffer[2]

buffer[3]

READER.PTR = &ReaderList

buffer[0]

buffer[1]

buffer[2]

buffer[3]

buffer[0]

buffer[1]

buffer[2]

buffer[3]

0x20000000 : ReaderList[0]

0x20000004 : ReaderList[1]

0x20000008 : ReaderList[2]

Figure 7: EasyDMA array list

4.8 AHB multilayer interconnect

On the AHB multilayer interconnect, the application CPU and all EasyDMA instances are AHB bus masters

while RAM, cache and peripherals are AHB slaves. External MCU subsystems can be seen both as master

and slave on the AHB multilayer interconnect.

Multiple AHB masters can access slave resources within the AHB multilayer interconnect as illustrated in

Memory on page 21. Access rights to each of the AHB slaves are resolved using the natural priority of

the different bus masters in the system.

4418_1315 v2.0

NRF9160-SICA-R7 Datasheet(PDF) 47 Page - Nordic Semiconductor