NRF9160-SICA-R7 datasheet(15/400 Pages) NORDIC

15 / 400 page

Product overview

nRF9160

AHB TO APB

BRIDGE

AHB multilayer

SPIM [0..3]

SAADC

GPIOTE

GPIO

UARTE [0..3]

TWIM [0..3]

SPIS [0..3]

EasyDMA

CPU

ARM

CORTEX-M33

AHB-AP

NVIC

ETM

SysTick

NVMC

RTC [0..1]

CODE

EasyDMA

TIMER [0..2]

EasyDMA

TWIS [0..3]

EasyDMA

DPPI

IPC

CLOCK

POWER

WDT

UICR

Debug

ETM trace ITM trace

I2S

PDM

EasyDMA

PWM[0..3]

EasyDMA

LTE-M modem

FICR

Clock control

ARM TrustZone

CryptoCell 310

DMA

KMU

REGULATORS

SPU

RAM0

RAM1

RAM2

RAM0

RAM1

RAM2

RAM3

master

slave

APB

(P0.0 – P0.31)

AIN0 – AIN7

AREF0 – AREF1

RTS

CTS

TXD

RXD

SCL

SDA

SCL

SDA

SCK

MOSI

MISO

SCK

MOSI

MISO

CSN

CLK

DIN

MCK

LRCK

SCL

SDOUT

SDIN

OUT0-OUT3

1.8 V USIM

USIM

RAM3

ANT - LTE

ANT - GPS

High frequency

clock sources

High frequency

clock sources

GPS

Figure 1: Block diagram

3.3 Peripheral interface

Peripherals are controlled by the CPU through configuration registers, as well as task and event registers.

Task registers are inputs, enabling the CPU and other peripherals to initiate a functionality. Event registers

are outputs, enabling a peripheral to trigger tasks in other peripherals and/or the CPU by tying events to

CPU interrupts.

4418_1315 v2.0

NRF9160-SICA-R7 Datasheet(PDF) 15 Page - Nordic Semiconductor

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