NRF9160-SICA-R7 datasheet(17/400 Pages) NORDIC

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Product overview

• Enforced peripheral behavior when switching between peripherals (disable the first peripheral before

enabling the second)

3.3.2 Peripherals with shared ID

In general (with the exception of ID 0), peripherals sharing an ID and base address may not be used

simultaneously. Only one peripheral can be enabled at a given ID.

When switching between two peripherals sharing an ID, the following should be performed to prevent

unwanted behavior:

1. Disable the previously used peripheral.

2. Disable any publish/subscribe connection to the DPPI system for the peripheral that is being disabled.

3. Clear all bits in the INTEN register, i.e. INTENCLR = 0xFFFFFFFF.

4. Explicitly configure the peripheral being enabled. Do not rely on inherited configuration from the

disabled peripheral.

5. Enable the now configured peripheral.

For a list of which peripherals that share an ID see Instantiation on page 24.

3.3.3 Peripheral registers

Most peripherals feature an ENABLE register. Unless otherwise specified, the peripheral registers must be

configured before enabling the peripheral.

PSEL registers need to be set before a peripheral is enabled or started. Updating PSEL registers while the

peripheral is running has no effect. In order to connect a peripheral to a different GPIO, the peripheral

must be disabled, the PSEL register updated, and the peripheral re-enabled. It takes four CPU cycles

between the PSEL register update and the connection between a peripheral and a GPIO becoming

effective.

Note: Note that the peripheral must be enabled before tasks and events can be used.

Most of the register values are lost during System OFF or when a reset is triggered. Some registers will

retain their values in System OFF or for some specific reset sources. These registers are marked as retained

in the register description for a given peripheral. For more information on their behavior, see chapter

Reset on page 56.

3.3.4 Bit set and clear

Registers with multiple single-bit bit fields may implement the set-and-clear pattern. This pattern enables

firmware to set and clear individual bits in a register without having to perform a read-modify-write

operation on the main register.

This pattern is implemented using three consecutive addresses in the register map, where the main

In the main register, the SET register sets individual bits and the CLR register clears them. Writing '1' to a

bit in the SET or CLR register will set or clear the same bit in the main register respectively. Writing '0' to a

bit in the SET or CLR register has no effect. Reading the SET or CLR register returns the value of the main

Note: The main register may not be visible and therefore not directly accessible in all cases.

3.3.5 Tasks

Tasks are used to trigger actions in a peripheral, such as to start a particular behavior. A peripheral can

implement multiple tasks with each task having a separate register in that peripheral's task register group.

4418_1315 v2.0

NRF9160-SICA-R7 Datasheet(PDF) 17 Page - Nordic Semiconductor