MPC8540 datasheet(204/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

4-18

Freescale Semiconductor

Reset, Clocking, and Initialization

4.4.3.10 RapidIO Transmit Clock Source

The RapidIO transmit clock source inputs, shown in Table 4-18, specify the source for the

RapidIO transmit clock. See Section 4.4.4.2, “RapidIO Clocks,” for more information. Note that

the value latched on this signal during POR is accessible through the memory-mapped

PORDEVSR (POR device status register) described in Section 18.4.1.4, “POR Device Status

4.4.3.11 RapidIO Device ID

The RapidIO device ID inputs, shown in Table 4-19, specify the 3 lower-order bits of the device

ID of the MPC8540 as used by RapidIO hosts. Note that the 5 high-order RapidIO device ID bits

cannot be set via POR configuration inputs. They may be initialized via the boot sequencer or by

the processor from boot ROM or by the RapidIO discovery process.

If configured as a RapidIO host, the upper order device ID bits default to zeros. If configured as a

RapidIO agent, the upper order device ID bits default to ones. Unconnected cfg_dev_IDn inputs

default to 1s regardless of the host/agent mode configuration.

Note that the value latched on this signal at POR is accessible through the memory-mapped

PORDEVSR described in Section 18.4.1.4, “POR Device Status Register (PORDEVSR).”

Table 4-17. TSEC2 Protocol Configuration

Functional

Signal

Reset

Configuration

Name

Value

(Binary

)

Meaning

TSEC2_TXD

Default (1)

cfg_tsec2

The TSEC2 controller operates using the GMII protocol (or RGMII if

configured in reduced mode as described in Section 4.4.3.7, “TSEC

Width”).

The TSEC2 controller operates using the TBI protocol (or RTBI if configured

in reduced mode as described in Section 4.4.3.7, “TSEC Width”) (default).

Table 4-18. RapidIO Transmit Clock Source

Functional

Signals

Reset Configuration

Name

Value

(Binary

)

Meaning

LGPL0,

LGPL1

Default (11)

cfg_rio_clk[0:1]

Reserved

The RapidIO receive clock is the source of the transmit clock.

The RapidIO transmit clock inputs (RIO_TX_CLK_IN and

RIO_TX_CLK) are the source of the transmit clock.

The CCB clock is the source of the transmit clock (default).

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