MPC8540 datasheet(208/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

4-22

Freescale Semiconductor

Reset, Clocking, and Initialization

4.4.3.20 Local Bus Output Hold Configuration

The LBC output hold configuration inputs, shown in Table 4-29, configure the output hold times

for the local bus interface output drivers. The default values are designed to meet the specified AC

timing requirements for the local bus. Hold times are adjusted by adding buffer delays to the

intrinsic delay of the output driver. Refer to the MPC8540 Integrated Processor Hardware

Specifications for specific timing information. Note that for three of the POR configuration input

settings, there is a minimum of one buffer of output hold delay between the LALE and LAD[0:31]

signals.

Table 4-27. PCI Output Hold Configuration (cfg_pci_mode = 1)

Functional

Signals

Reset Configuration

Name

Value

(Binary

)

Meaning

LWE[0:1]

Default (11)

cfg_pci_hold[0:1]

Two added buffer delays—required to meet 2-ns hold time requirement

Three added buffer delays (default + 1)

Zero added buffer delays (default + 2 mod 4)

One added buffer delay (default + 3 mod 4)

Table 4-28. PCI-X Output Hold Configuration (cfg_pci_mode = 0)

Functional

Signals

Reset Configuration

Name

Value

(Binary

)

Meaning

LWE[0:1]

Default (11)

cfg_pci_hold[0:1]

Zero added buffer delays—meets 0.7 ns hold time requirement

One added buffer delay (default + 1)

Two added buffer delays (default + 2)

Three added buffer delays (default + 3)

Table 4-29. Local Bus Output Hold Configuration

Functional

Signals

Reset Configuration

Name

Value

(Binary

)

Meaning

TSEC2_TXD[6:5

]

Default (11)

cfg_lb_hold[0:1]

One added buffer delay (default)

(zero added buffer delays for LALE)

Two added buffer delays (default + 1)

(one added buffer delay for LALE)

Three added buffer delays (default + 2)

(one added buffer delay for LALE)

Zero added buffer delays

(zero added buffer delays for LALE)

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