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MPC8540 Datasheet(PDF) 212 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 212 Page - Freescale Semiconductor, Inc |
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212 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 4-26 Freescale Semiconductor Reset, Clocking, and Initialization Figure 4-8. RTC and Core Timer Facilities Clocking Options RTC (Sampled and Synchronized) HID0 TBEN SEL_TBCLK Core Time Base (Incrementer) Decrementer Event 63 DECAR 32 Auto-Reload 63 32 63 32 (Decrementer) Watchdog timer events based on one of the 64 TB bits selected by concatenating TCR[WPEXT] with the EIS-defined TCR[WP] (WPEXT||WP). DEC TBU TBL Core Timer e500 Core 8 ÷ CCB Clock • • • • • • Note: The logic circuits shown depict functional relationships only; they do not represent physical implementation details. (0 ⇒ 1 Detect) Facilities Clock Fixed-interval timer events based on one of the 64 TB bits selected by concatenating TCR[FPEXT] with the EIS-defined TCR[FP] (FPEXT||FP). |
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