MPC8540 datasheet(210/1302 Pages) FREESCALE

210 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

4-24

Freescale Semiconductor

Reset, Clocking, and Initialization

Figure 4-6. Clock Subsystem Block Diagram

When the PCI/PCI-X interface is being used, SYSCLK also functions as the PCI_CLK signal.

Note that this is true both when the MPC8540 is in agent mode and host mode. The MPC8540 does

not provide a separate PCI_CLK output in host mode.

4.4.4.2

RapidIO Clocks

As shown in Figure 4-7, the RapidIO transmit clocks (RIO_TCLK and RIO_TCLK) can be

selected from one of three sources. If the desired RapidIO clock is sourced by the device to which

the MPC8540 RapidIO port is connected, then the transmit clock can be derived from the receive

clock (RIO_RCLK and RIO_RCLK).

Figure 4-7. RapidIO Transmit Clock Options

LCLK2

Core PLL

Device PLL

DLL

MSYNC_IN

LSYNC_IN

LSYNC_OUT

LCLK0

LCLK1

MSYNC_OUT

MCK[0:5]

core_clk

e500 Core

CCB_clk to Rest of the Device

SYSCLK/

PCI_CLK

CCB_clk

cfg_sys_pll[0:3]

cfg_core_pll[0:1]

MPC8540

DDR

Controller

LBC

CCB_clk

RIO_RCK

RIO_TCK

cfg_rio_clk[0:1]

Clock

Synthesis

Chip

RIO_TX_CLK_IN

MPC8540

MPC8540 Datasheet(PDF) 210 Page - Freescale Semiconductor, Inc

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