MPC8540 datasheet(209/1302 Pages) FREESCALE

209 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

4-23

4.4.3.21 General-Purpose POR Configuration

The LBC address/data bus inputs, shown in Table 4-30, configure the value of the general-purpose

POR configuration register defined in Section 18.4.1.6, “General-Purpose POR Configuration

A value placed on LAD[0:31] during POR is captured and stored (read only) in the GPPORCR.

Software can then use this value to inform the operating system about initial system configuration.

Typical interpretations include circuit board type, board ID number, or a list of available

peripherals.

4.4.4

Clocking

The following paragraphs describe the clocking within the MPC8540 device.

4.4.4.1

System Clock/PCI Clock

The MPC8540 takes a single input clock, SYSCLK, as its primary clock source for the e500 core

and all of the devices and interfaces that operate synchronously with the core. As shown in

Figure 4-6, the SYSCLK input (frequency) is multiplied up using a phase lock loop (PLL) to create

the core complex bus (CCB) clock (also called the platform clock). The CCB clock is used by

virtually all of the synchronous system logic, including the L2 cache, and other internal blocks

such as the DMA and interrupt controller. The CCB clock also feeds the PLL in the e500 core and

the DLLs that create clocks for the DDR SDRAM and local bus memory controllers. Note that the

divide-by-two CCB clock divider and the divide-by-n CCB clock divider, shown in Figure 4-6, are

located in the DDR and local bus blocks, respectively.

Table 4-30. General-Purpose POR Configuration

Functional

Signals

Reset

Configuration

Name

Value

(Binary

)

Meaning

LAD[0:31]

No default

cfg_gpporcr

General-purpose POR configuration vector to be placed in GPPORCR

MPC8540 Datasheet(PDF) 209 Page - Freescale Semiconductor, Inc