MPC8540 datasheet(197/1302 Pages) FREESCALE

197 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

4-11

Figure 4-5 shows a timing diagram of the POR sequence.

Figure 4-5. Power-On Reset Sequence

4.4.3

Power-On Reset Configuration

Various device functions are initialized by sampling certain signals during the assertion of

HRESET. The values of all these signals are sampled into registers while HRESET is asserted.

These inputs are to be pulled high or low by external resistors. During HRESET, all other signal

drivers connected to these signals must be in the high-impedance state.

Most POR configuration signals have internal pull-up resistors so that if the desired setting is high,

there is no need for a pull-up resistor on the board. Other POR configuration signals do not use

pull-ups and, therefore, must be pulled high or low. Refer to the MPC8540Integrated Processor

Hardware Specifications for proper resistor values to be used for pulling POR configuration

signals high or low.

This section describes the functions and modes configured by POR configuration signals. Note

that many reset configuration settings are accessible to software through the following read-only

memory-mapped registers described in Chapter 18, “Global Utilities.”

SYSCLK

HRESET

TRESET

SRESET

(high impedance)

HRESET_REQ

POR Configs

PLL Configs

READY1

ASLEEP

(High Impedance)

1 Multiplexed with TRIG_OUT.

MPC8540 Datasheet(PDF) 197 Page - Freescale Semiconductor, Inc