STM32W108HB datasheet(148/278 Pages) STMICROELECTRONICS

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Serial interfaces

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

9.12.13

Serial controller DMA control register (SCx_DMACR)

Address offset: 0xC830 (SC1_DMACR) and 0xC030 (SC2_DMACR)

Reset value:

0x0000 0000

Reserved, must be kept at reset value

TXRST:

RXRST:

TXLODB:

TXLODA:

RXLODB:

RXLODA:

Reserved

TXRST

RXRST

LODB

LODA

LODB

LODA

Bits [31:6]

Bit 5

Setting this bit resets the transmit DMA. This bit clears automatically.

Bit 4

Setting this bit resets the receive DMA. This bit clears automatically.

Bit 3

Setting this bit loads DMA transmit buffer B addresses and allows the DMA controller to start

processing transmit buffer B. If both buffer A and B are loaded simultaneously, buffer A is

used first. This bit is cleared when DMA completes. Writing a zero to this bit has no effect.

Reading this bit returns DMA buffer status:

0: DMA processing is complete or idle

1: DMA processing is active or pending

Bit 2

Setting this bit loads DMA transmit buffer A addresses and allows the DMA controller to start

processing transmit buffer A. If both buffer A and B are loaded simultaneously, buffer A is

used first. This bit is cleared when DMA completes. Writing a zero to this bit has no effect.

Reading this bit returns DMA buffer status:

0: DMA processing is complete or idle

1: DMA processing is active or pending

Bit 1

Setting this bit loads DMA receive buffer B addresses and allows the DMA controller to start

processing receive buffer B. If both buffer A and B are loaded simultaneously, buffer A is used

first. This bit is cleared when DMA completes. Writing a zero to this bit has no effect. Reading

this bit returns DMA buffer status:

0: DMA processing is complete or idle

1: DMA processing is active or pending

Bit 0

Setting this bit loads DMA receive buffer A addresses and allows the DMA controller to start

processing receive buffer A. If both buffer A and B are loaded simultaneously, buffer A is used

first. This bit is cleared when DMA completes. Writing a zero to this bit has no effect. Reading

this bit returns DMA buffer status:

0: DMA processing is complete or idle

1: DMA processing is active or pending

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