STM32W108HB datasheet(236/278 Pages) STMICROELECTRONICS

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Interrupts

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

The NVIC also contains a software-configurable interrupt prioritization mechanism. The

Reset, NMI, and Hard Fault exceptions, in that order, are always the highest priority, and are

not software-configurable. All other exceptions can be assigned a 5-bit priority number, with

low values representing higher priority. If any exceptions have the same software-

configurable priority, then the NVIC uses the hardware-defined priority. The hardware-

defined priority number is the same as the position of the exception in the exception table.

For example, if IRQA and IRQB both fire at the same time and have the same software-

defined priority, the NVIC handles IRQA, with priority number 28, first because it has a

higher hardware priority than IRQB with priority number 29.

For further information on the NVIC and Cortex-M3 exceptions, refer to the ARM® Cortex-

M3 Technical Reference Manual and the ARM ARMv7-M Architecture Reference Manual.

12.2

Management interrupt registers

12.2.1

Management interrupt source register (MGMT_ISR)

Address offset: 0x4000 A018

Reset value:

0x0000 0000

Reserved, must be kept at reset value

HSECOMPHLIF: OSC24M_HI interrupt

HSECOMPLLIF: OSC24M_LO interrupt

Reserved

HSE

COMPH

LIF

HSE

COMPL

LIF

Bits [31:2]

Bit 1

Bit 0

STM32W108HB Datasheet(PDF) 236 Page - STMicroelectronics